Duixian Liu - Antenna-in-Package Technology and Applications

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A comprehensive guide to antenna design, manufacturing processes, antenna integration, and packaging Antenna-in-Package Technology and Applications • Includes a brief history of antenna-in-package technology • Describes package structures widely used in AiP, such as ball grid array (BGA) and quad flat no-leads (QFN) • Explores the concepts, materials and processes, designs, and verifications with special consideration for excellent electrical, mechanical, and thermal performance
Written for students in electrical engineering, professors, researchers, and RF engineers, 
 offers a guide to material selection for antennas and packages, antenna design with manufacturing processes and packaging constraints, antenna integration, and packaging.

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Giancarlo Fortino Andreas Molisch Diomidis Spinellis
David Alan Grier Saeid Nahavandi Elya B. Joffe
Donald Heirman Ray Perez Sarah Spurgeon
Xiaoou Li Jeffrey Reed Ahmet Murat Tekalp

Antenna-in-Package Technology and Applications

Edited by

Duixian Liu

IBM Thomas J. Watson Research Center

New York, USA

Yueping Zhang

School of Electrical and Electronic Engineering

Nanyang Technological University, Singapore

Copyright 2020 by The Institute of Electrical and Electronics Engineers Inc - фото 13

Copyright © 2020 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

Published by John Wiley & Sons, Inc., Hoboken, New Jersey.

Published simultaneously in Canada.

No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per‐copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750‐8400, fax (978) 750‐4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748‐6011, fax (201) 748‐6008, or online at http://www.wiley.com/go/permission.

Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages.

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Library of Congress Cataloging‐in‐Publication data applied for

ISBN: 9781119556633

Cover Design: Wiley

Cover Image: © windwheel/Shutterstock

List of Contributors

Yueping Zhang

School of Electrical and Electronic Engineering

Nanyang Technological University

Singapore

Ning Ye

Package Technology Development & Integration

Milpitas

USA

Xiaoxiong Gu

Thomas. J. Watson Research Center, IBM

New York

USA

Pritish Parida

Thomas. J. Watson Research Center, IBM

New York

USA

A.C.F. Reniers

Department of Electrical Engineering

Eindhoven University of Technology (TU/e)

Eindhoven

The Netherlands

U. Johannsen

Department of Electrical Engineering

Eindhoven University of Technology (TU/e)

Eindhoven

The Netherlands

A.B. Smolders

Department of Electrical Engineering

Eindhoven University of Technology (TU/e)

Eindhoven

The Netherlands

Atif Shamim

Computer, Electrical and Mathematical Sciences and Engineering Division

King Abdullah University of Science & Technology (KAUST)

KSA

Haoran Zhang

Computer, Electrical and Mathematical Sciences and Engineering Division

King Abdullah University of Science & Technology (KAUST)

KSA

Frédéric Gianesello

ST Microelectronics

Technology R&D

Silicon Technology Development

Crolles

France

Diane Titz

Université Nice Sophia Antipolis

Polytech'Lab

Biot

France

Cyril Luxey

Université Nice Sophia Antipolis

Polytech'Lab

Biot

France

Maciej Wojnowski

Infineon Technologies AG

Neubiberg

Germany

Klaus Pressel

Infineon Technologies AG

Regensburg

Germany

Tong‐Hong Lin

The School of Electrical and Computer Engineering

Georgia Institute of Technology

Atlanta

USA

Ryan A. Bahr

The School of Electrical and Computer Engineering

Georgia Institute of Technology

Atlanta

USA

Manos M. Tentzeris

The School of Electrical and Computer Engineering

Georgia Institute of Technology

Atlanta

USA

Duixian Liu

Thomas. J. Watson Research Center, IBM

New York

USA

Amin Enayati

Emerson & Cuming Anechoic Chambers

Antwerp Area

Belgium

Karin Mohammadpour‐Aghdam

School of Electrical and Computer Engineering

University of Tehran

Iran

Farbod Molaee‐Ghaleh

School of Electrical and Computer Engineering

University of Tehran

Iran

Preface

Rapid advances in semiconductor and packaging technologies have promoted the development of two system design concepts known as system on chip (SoC) and system‐in‐package (SiP). SoC integrates analog, digital, mixed‐signal, and radio frequency (RF) circuits on a chip by a semiconductor process, while SiP implements separately manufactured functional blocks in a package by a packaging process. SoC yields improved system reliability and functionality at a much lower system cost. However, it degrades system performance and increase system power consumption due to unavoidable compromises in every circuit type in order to use the same material and process. On the contrary, SiP enhances system performance and reduces system power consumption but results in lower system reliability and higher system cost because of functional blocks and the fabrication of the package with different materials and processes.

Antennas are essential components for wireless systems. It is known that antennas are difficult to miniaturize, let alone integrate. Nevertheless, there have been attempts to integrate an antenna (or antennas) with other circuits in a die on a wafer using the back end of the line. An antenna realized in such a way is called an antenna on a chip (AoC) and is more suitable for terahertz applications for cost and performance reasons. In addition, there have been studies to integrate an antenna (or antennas) with a radio or radar die (or dies) into a standard surface‐mounted device using a packaging process, which has created a new trend in antenna and packaging termed antenna‐in‐package (AiP). AoC and AiP are obviously subsets of the above SoC and SiP concepts, so why do we specifically differentiate them from SoC and SiP? The reason is to highlight their unique property of radiation.

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