King-Ning Tu - Electronic Packaging Science and Technology

1 Cover

2 Title Page

3 Copyright Page

4 Preface

5 1 Introduction1.1 Introduction 1.2 Impact of Moore’s Law on Si Technology 1.3 5G Technology and AI Applications 1.4 3D IC Packaging Technology 1.5 Reliability Science and Engineering 1.6 The Future of Electronic Packaging Technology 1.7 Outline of the Book References

6 Part I: 2 Cu‐to‐Cu and Other Bonding Technologies in Electronic Packaging2.1 Introduction 2.2 Wire Bonding 2.3 Tape‐Automated Bonding 2.4 Flip‐Chip Solder Joint Bonding 2.5 Micro‐Bump Bonding 2.6 Cu‐to‐Cu Direct Bonding 2.7 Hybrid Bonding 2.8 Reliability – Electromigration and Temperature Cycling Tests Problems References 3 Randomly‐Oriented and (111) Uni‐directionally‐Oriented Nanotwin Copper3.1 Introduction 3.2 Formation Mechanism of Nanotwin Cu 3.3 In Situ Measurement of Stress Evolution During Nanotwin Deposition 3.4 Electrodeposition of Randomly Oriented Nanotwinned Copper 3.5 Formation of Unidirectionally (111)‐oriented Nanotwin Copper 3.6 Grain Growth in [111]‐Oriented nt‐Cu 3.7 Uni‐directional Growth of η‐Cu 6Sn 5in Microbumps on (111) Oriented nt‐Cu 3.8 Low Thermal‐Budget Cu‐to‐Cu Bonding Using [111]‐Oriented nt‐Cu 3.9 Nanotwin Cu RDL for Fanout Package and 3D IC Integration Problems References 4 Solid–Liquid Interfacial Diffusion Reaction (SLID) Between Copper and Solder4.1 Introduction 4.2 Kinetics of Scallop‐Type IMC Growth in SLID 4.3 A Simple Model for the Growth of Mono‐Size Hemispheres 4.4 Theory of Flux‐Driven Ripening 4.5 Measurement of the Nano‐channel Width Between Two Scallops 4.6 Extremely Rapid Grain Growth in Scallop‐Type Cu6Sn5 in SLID Problems References 5 Solid‐State Reactions Between Copper and Solder5.1 Introduction 5.2 Layer‐Type Growth of IMC in Solid‐State Reactions 5.3 Wagner Diffusivity 5.4 Kirkendall Void Formation in Cu 3Sn 5.5 Sidewall Reaction to Form Porous Cu 3Sn in μ‐Bumps 5.6 Effect of Surface Diffusion on IMC Formation in Pillar‐Type μ‐Bumps Problems References

7 Part II: 6 Essence of Integrated Circuits and Packaging Design6.1 Introduction 6.2 Transistor and Interconnect Scaling 6.3 Circuit Design and LSI 6.4 System‐on‐Chip (SoC) and Multicore Architectures 6.5 System‐in‐Package (SiP) and Package Technology Evolution 6.6 3D IC Integration and 3D Silicon Integration 6.7 Heterogeneous Integration: An Introduction Problems References 7 Performance, Power, Thermal, and Reliability7.1 Introduction 7.2 Field‐Effect Transistor and Memory Basics 7.3 Performance: A Race in Early IC Design 7.4 Trend in Low Power 7.5 Trade‐off between Performance and Power 7.6 Power Delivery and Clock Distribution Networks 7.7 Low‐Power Design Architectures 7.8 Thermal Problems in IC and Package 7.9 Signal Integrity and Power Integrity (SI/PI) 7.10 Robustness: Reliability and Variability Problems References 8 2.5D/3D System‐in‐Packaging Integration8.1 Introduction 8.2 2.5D IC: Redistribution Layer (RDL) and TSV‐Interposer 8.3 2.5D IC: Silicon, Glass, and Organic Substrates 8.4 2.5D IC: HBM on Silicon Interposer 8.5 3D IC: Memory Bandwidth Challenge for High‐Performance Computing 8.6 3D IC: Electrical and Thermal TSVs 8.7 3D IC: 3D‐Stacked Memory and Integrated Memory Controller 8.8 Innovative Packaging for Modern Chips/Chiplets 8.9 Power Distribution for 3D IC Integration 8.10 Challenge and Trend Problems References

8 Part III: 9 Irreversible Processes in Electronic Packaging Technology9.1 Introduction 9.2 Flow in Open Systems 9.3 Entropy Production 9.4 Cross‐Effects in Irreversible Processes 9.5 Cross‐Effect Between Atomic Diffusion and Electrical Conduction 9.6 Irreversible Processes in Thermomigration 9.7 Cross‐Effect Between Heat Conduction and Electrical Conduction Problems References 10 Electromigration10.1 Introduction 10.2 To Compare the Parameters in Atomic Diffusion and Electric Conduction 10.3 Basic of Electromigration 10.4 Current Crowding and Electromigration in 3‐Dimensional Circuits 10.5 Joule Heating and Heat Dissipation Problems References 11 Thermomigration11.1 Introduction 11.2 Driving Force of Thermomigration 11.3 Analysis of Heat of Transport, Q* 11.4 Thermomigration Due to Heat Transfer Between Neighboring Pairs of Powered and Unpowered Solder Joints Problems References 12 Stress‐Migration12.1 Introduction 12.2 Chemical Potential in a Stressed Solid 12.3 Stoney’s Equation of Biaxial Stress in Thin Films 12.4 Diffusional Creep 12.5 Spontaneous Sn Whisker Growth at Room Temperature 12.6 Comparison of Driving Forces Among Electromigration, Thermomigration, and Stress‐Migration Problems References 13 Failure Analysis13.1 Introduction 13.2 Microstructure Change with or Without Lattice Shift 13.3 Statistical Analysis of Failure 13.4 A Unified Model of MTTF for Electromigration, Thermomigration, and Stress‐Migration 13.5 Failure Analysis in Mobile Technology Problems References 14 Artificial Intelligence in Electronic Packaging Reliability14.1 Introduction 14.2 To Change Time‐Dependent Event to Time‐Independent Event 14.3 To Deduce MTTF from Mean Microstructure Change to Failure 14.4 Summary

9 Index

10 End User License Agreement

1 Chapter 1 Table 1.1 5G technical requirements.

2 Chapter 2 Table 2.1 Cu surface diffusivity (cm 2/sec).

3 Chapter 6Table 6.1 Ideal scaling of MOS transistors.Table 6.2 Scaling of local and global interconnections.Table 6.3 Intel’s P856 Interconnect dimensions (0.25 um process).

4 Chapter 10Table 10.1 Comparison between atomic flux and electron flux.Table 10.2 Diffusivity at 100 °C.

1 Chapter 1 Figure 1.1 A sketch of the achievements of 2D IC of Si technology according ... Figure 1.2 An image of part of the device structure of the mainframe compute... Figure 1.3 The petals of flower, which shows the required functions in 4G an... Figure 1.4 Scanning electron microscopy (SEM) image of the cross‐section of ... Figure 1.5 (a) Synchrotron radiation tomographic images of a similar device ... Figure 1.6 Schematic diagram of the cross‐section of a typical 3D IC device.... Figure 1.7 An example of electromigration electromigration‐induced failure o...

2 Chapter 2 Figure 2.1 General process of packaging procedure with lead‐frame. Figure 2.2 Photo for lead‐frames. Figure 2.3 First and second bonds in ultrasonic wire bonding. Figure 2.4 General layout of tape circuit boards. Sprocket holes guide the t... Figure 2.5 Tape‐automated bonding procedure. Inner lead bonds connect die to... Figure 2.6 Schematic diagram of gang bonding. A press applies force to multi... Figure 2.7 Schematic diagram of flipping chip to form bonds at multiple sold... Figure 2.8 Schematic diagram of the cross‐section of a ceramic module joined... Figure 2.9 Schematic diagram of the cross‐section of a C4 flip‐chip solder j... Figure 2.10 Schematic diagram of the formation of a C‐4 solder joint of sold... Figure 2.11 Schematic diagram of automatic self‐alignment process in the ref... Figure 2.12 Schematic diagrams of the procedure in flip‐chip solder joint te... Figure 2.13 Schematic diagram of the distribution of C‐4 solder joint on the... Figure 2.14 Schematic diagram of the peripheral distribution I/O connections... Figure 2.15 Schematic diagram and SEM image of Cu/solder/Cu micro‐bump. Figure 2.16 SEM cross‐sectional image of side‐wall wetting and porous Cu 3Sn ... Figure 2.17 A plot of the I/O number per chip vs. various types of bonding t... Figure 2.18 Effect of surface roughness on minimum bonding temperature. Figure 2.19 Schematic diagram of the Cu‐to‐Cu interface. (a) The stress grad... Figure 2.20 The surface morphology of a Cu surface analyzed by atomic force ... Figure 2.21 (a) It shows the effect of surface roughness on the bonding time... Figure 2.22 Cross‐sectional TEM images of voids in the Cu‐to‐Cu bonding inte... Figure 2.23 (a) Plan‐view of TEM image of voids in the Cu‐to‐Cu bonding inte... Figure 2.24 Kagawa et al. presented their void distribution for the Cu‐to‐Cu... Figure 2.25 (a) A high‐resolution TEM image for a low‐angle grain boundary a... Figure 2.26 Cross‐sectional focus ion beam (FIB) and electron back‐scatter d... Figure 2.27 A plot of shear strength against bonding temperature of Cu pilla... Figure 2.28 Schematic diagrams depict the effect of Cu dishing on hybrid bon... Figure 2.29 Cross‐sectional SEM image of Cu interconnects with a pitch of ap... Figure 2.30 It shows state‐of‐the‐art of hybrid Cu‐to‐Cu bonds using the SiC... Figure 2.31 It shows the microstructures for a Cu‐to‐Cu joint after 1000 cyc...