King-Ning Tu - Electronic Packaging Science and Technology

3 Chapter 3Figure 3.1 High resolution TEM images showing the atom migration under elect...Figure 3.2 Schematic diagram of the periodic nanotwin structure by repetitio...Figure 3.3 Biaxial stress in the model of calculation.Figure 3.4 (a) Calculated curves showing the evolution of the total energies...Figure 3.5 Schematic diagram depicts the in situ stress measurement system. ...Figure 3.6 The evolution of the product of stress and film thickness as a fu...Figure 3.7 Microstructures of pulsed electrodeposited randomly oriented nt‐C...Figure 3.8 The schematic drawing for dislocation slip between two parallel t...Figure 3.9 (a) FIB images of the both the top view and cross‐sectional view ...Figure 3.10 Plan‐view EBSD showing the orientation of surface grains of the ...Figure 3.11 Cross‐sectional FIB image of an electroplated [111]‐oriented nan...Figure 3.12 Grain growth in [111] nt‐Cu film. Cross‐sectional FIB images for...Figure 3.13 Transformation of the oriented (111) nt‐Cu to large grain (100) C...Figure 3.14 The growth of large (100) grains from the oriented (111) nt‐Cu. ...Figure 3.15 (a) Cross‐sectional EBSD orientation image map for a SnAg micro‐...Figure 3.16 Microstructures after solid‐state aging of nt‐Cu/solder/nt‐Cu at...Figure 3.17 Cross‐sectional FIB image showing the microstructures of nt‐Cu f...Figure 3.18 Schematic diagram of a void in the bonding interface. Under ther...Figure 3.19 Microstructures analysis of the bonding interface for a [111] nt...Figure 3.20 Schematic drawing for a fanout package. A chip is embedded in ep...Figure 3.21 Tensile stress and strain curves for regular Cu and nt‐Cu films ...Figure 3.22 Plot of yield strength against electrical and thermal conductivi...Figure 3.23 Voids and oxidation formation in the nt‐Cu line after current st...

4 Chapter 4Figure 4.1 (a) A circular solder mount or cap on a copper substrate. (b) The...Figure 4.2 A schematic diagram of the cross‐section on an array of hemispher...Figure 4.3 The physical meaning of C band C eare, respectively, the equilibr...Figure 4.4 A plot of φ(η) versus η.Figure 4.5 In a sample having a very thin layer of Sn, when the Sn was compl...Figure 4.6 SEM image of the opposite rows of IMC in a micro‐bump solder join...Figure 4.7 (a) After reflow at 260 C for four minutes of the same SnAg solde...

5 Chapter 5Figure 5.1 The growth of a single IMC phase, the “i” phase, between two term...Figure 5.2 Free energy diagram of A (α‐phase) and B (β‐phase), and an IMC (i...Figure 5.3 SEM image of the distribution of Kirkendall voids in the layer of...Figure 5.4 A set of SEM cross‐sectional images of micro‐bumps after annealin...Figure 5.5 A schematic diagram of cellular precipitation is shown. The cell ...Figure 5.6 A schematic diagram of the growth of porous Cu 3Sn is shown, where...Figure 5.7 The pillar‐type samples are shown having various diameters, from ...Figure 5.8 SEM images of 1 1 μm pillars after annealing at 195 °C for (a) 30...Figure 5.9 (a and b) The change of IMC thickness with different diameters wh...Figure 5.10 The mechanism of Cu interstitial diffusion into 1 μm pillar is d...

6 Chapter 6Figure 6.1 IC design style: full‐custom.Figure 6.2 IC design style: standard cell (row‐based).Figure 6.3 IC design style: field programmable gate array (FPGA).Figure 6.4 VLSI design process and flow.Figure 6.5 Evolution of minimum feature sizes in semiconductor manufacturing...Figure 6.6 Wire bonding in a BGA.Figure 6.7 Flip chip bonding packages.Figure 6.8 The package evolution: from MCM to HI.

7 Chapter 7Figure 7.1 The trend of power density along the process advances.Figure 7.2 (a) Cross section of an n‐type transistor. (b) Basic DRAM cell.Figure 7.3 An n‐type transistor with channel length (L) and width (W) [3].Figure 7.4 DRAM cell and block configurations [4]. (a) Schematic circuit for...Figure 7.5 A typical 6T Static RAM cell.Figure 7.6 Illustration of the performance/timing analysis in digital design...Figure 7.7 Illustration of energy‐delay product (EDP) for the trade‐off.Figure 7.8 A power network illustration.Figure 7.9 A clock mesh/tree hybrid architecture for clock network.Figure 7.10 An example of DVFS architecture chip.Figure 7.11 Illustration of MSV designs.Figure 7.12 In MSV designs, level shifters are needed for the signal traveli...Figure 7.13 (a) Temperature distribution of a testcase using the thermal mod...

8 Chapter 8Figure 8.1 Packaging hierarchy in interposer‐based 3D IC. CoWoS is one of th...Figure 8.2 An illustration for high bandwidth memory (HBM) with interposer....Figure 8.3 TSV fabrication options in 3D IC integration: via‐first, via‐midd...Figure 8.4 Process flow of DRAM/logic die stacking module in [16]: (a) a thi...Figure 8.5 Cross‐sectional view of single chip InFO_PoP with TIV (Through‐In...Figure 8.6 3D power delivery model illustration.

9 Chapter 9Figure 9.1 (a) It depicts a closed container keeping a fixed amount of water...Figure 9.2 Two heat chambers at temperature of T 1and T 2, where the temperat...Figure 9.3 Schematic diagram depicting electric conduction in a conductor of...Figure 9.4 (a) Schematic diagram of flip chip technology, in which typically...Figure 9.5 Schematic diagram depicting one‐dimensional heat conduction. Let ...Figure 9.6 (a) SEM images of a set Al short stripes in electromigration. The...Figure 9.7 Schematic diagram of a short Al strip patterned on a baseline of ...Figure 9.8 Schematic diagram to depict a vacancy concentration gradient decr...Figure 9.9 (a) Schematic diagram of a flip chip on a substrate, (b) the cros...Figure 9.10 SEM cross‐sectional images of composite solder bump before and a...Figure 9.11 (a) Schematic diagram depicts a row of 24 solder bumps from righ...Figure 9.12 (a) Schematic diagram depicts a single metal wire of a given len...

10 Chapter 10Figure 10.1 Schematic diagram depicting atomic diffusion in a face‐centered‐...Figure 10.2 (a) SEM image of a straight Ni silicide line formed between two ...Figure 10.3 (a) Schematic diagram of the cross‐section of an Al short stripe...Figure 10.4 The lower schematic diagram (b), depicting a joint of an Al line...Figure 10.5 (a) Schematic diagram of an in situ TEM samples, where the elect...Figure 10.6 (a) Schematic diagram depicts a Cu interconnect conductor with a...Figure 10.7 (a) The schematic diagram on the left side depicts a conductor w...Figure 10.8 The upper row of SEM images shows a daisy chain of flip‐chip sol...

11 Chapter 11Figure 11.1 We shall consider J in the equation between two points; point 1 ...Figure 11.2 The temperature distribution on the cross‐section of a solder jo...Figure 11.3 (a) Schematic diagram of a row of four composite solders, in whi...

12 Chapter 12Figure 12.1 (a) The deposition of an Al thin film on a thick quartz substrat...Figure 12.2 (a) It shows that the stresses act along the two principal axes ...Figure 12.3 (a) We have enlarged one end of the substrate to show the neutra...Figure 12.4 A hexagonal grain in a polycrystalline solid is under a shear st...Figure 12.5 (a) SEM image of a Sn whisker between two Cu bumps having a top ...Figure 12.6 (a) SEM image of Sn whiskers on a lead‐frame surface. (b) A shor...Figure 12.7 Both (a) and (b) are electron diffraction pattern and cross‐sect...Figure 12.8 A cross‐sectional view of a whisker on a bilayer of Sn/Cu. A cra...Figure 12.9 SEM image of a Sn whisker on a leg of lead‐frame indicated by a ...Figure 12.10 Synchrotron radiation micro‐diffraction was used to measure the...Figure 12.11 The measured distribution of compressive stress in the surround...Figure 12.12 To model the whisker growth, we assume an array of them, each h...Figure 12.13 A set of four SEM images of the initiation and growth of a Sn w...

13 Chapter 13Figure 13.1 Shows such an equipment for statistical analysis of failure of f...Figure 13.2 Shows an optical image of such a test board having four chips on...Figure 13.3 The layout of the solder joints between the chip and the board i...Figure 13.4 Is a schematic diagram to illustrate the idea of lattice shift....Figure 13.5 Shows the Weibull distribution plots of time to failure of a set...Figure 13.6 All the failures showed a rather flat resistance change with tim...Figure 13.7 (a) and (b) show the failure site images of the sample failed in...Figure 13.8 (a) It shows that the location of RDL in the sample is near the ...Figure 13.9 Simulation result in three different stressing conditions, from ...Figure 13.10 (a) Cross‐sectional SEM image showing the test sample, (b) Top ...Figure 13.11 In the test structure, there are two Si chips placed horizontal...