Liliana Andrade - Multi-Processor System-on-Chip 1

Figure 2.17. KaNN augmented computation graph

High-integrity computing on the MPPA3 processor refers to applications that execute in a physically isolated domain of the processor, whose functions are developed under model-based design and must meet hard real-time constraints. The Research Open-Source Avionics and Control Engineering (ROSACE) case study introduced the model-based design of avionics applications that targeted multi-core platforms (Pagetti et al . 2014). The model-based design for the MPPA processor focuses on mono-periodic and multi-periodic harmonic applications (Figure 2.18) that are described using the Lustre (Halbwachs et al . 1991) or the SCADE Suite 5 synchronous dataflow languages (Graillat et al . 2018, 2019). The execution environment is composed of one or more clusters configured for asymmetric multi-processing ( section 2.3.2), where each core is logically associated with one SMEM bank, and where tasks run to completion.

Figure 2.18. ROSACE harmonic multi-periodic case study (Graillat et al. 2018)

The code generation workflow assumes that some nodes of the synchronous dataflow program are identified by the programmer as concurrent tasks, and defines the implicit top-level “root” task. A Lustre or SCADE Suite high-level compiler generates C-code for this set of tasks, communicating and synchronizing through one-to-one channels. Channels correspond to single-producer, single-consumer FIFOs of depth one, whose implementation is abstracted form the task C-code under SEND and RECV macros. The rest of the code generation workflow involves:

– providing workers, each able to execute a set of tasks sequentially;

– scheduling and mapping the set of tasks on the workers;

– implementing the communication channels and their SEND/RECV methods;

– compiling C-code with the CompCert formally verified compiler.

In the MPPA workflow, the workers are the PEs associated with a memory bank.

Timing verification follows the principles of the multi-core response time analysis (MRTA) framework (Davis et al . 2018). Starting from the task graph, its mapping to PEs, and given the worst-case execution time (WCET) of each task in isolation, the multi-core inference analysis (MIA) tool (Rihani et al . 2016; Dupont de Dinechin et al . 2020) refines the execution intervals of each task while updating its WCET for interference on the shared resources. The MIA tool relies on the property that the PEs, the memory hierarchy and the interconnects are timing-compositional. The refined release dates are used to activate a fast hardware release mechanism for each task. A task then executes when its input channels are data-ready (Figure 2.19).

Figure 2.19. MCG code generation of the MPPA processor

We introduced the third-generation MPPA processor, which implements a many-core architecture that targets intelligent systems, defined as cyber-physical systems enhanced with high-performance machine learning capabilities and strong cyber-security support. As with the GPGPU architecture, the MPPA3 architecture is composed of a number of multi-core compute units that share the processor external memory and I/O through on-chip global interconnects. However, the MPPA architecture is able to host standard software, offers excellent time predictability and provides strong partitioning capabilities. This enables us to consolidate, on a single or dual processor platform, the high-performance machine learning and computer vision functions implied by vehicle perception, the high-integrity functions developed through model-based design, and the cyber-security functions required by secured communications.

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