Liliana Andrade - Multi-Processor System-on-Chip 2

1 Cover

2 Title Page SCIENCES Electronics Engineering , Field Director – Francis Balestra Design Methodologies and Architecture , Subject Head – Ahmed Jerraya

3 Copyright First published 2020 in Great Britain and the United States by ISTE Ltd and John Wiley & Sons, Inc. Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address: ISTE Ltd 27-37 St George’s Road London SW19 4EU UK www.iste.co.uk John Wiley & Sons, Inc. 111 River Street Hoboken, NJ 07030 USA www.wiley.com © ISTE Ltd 2020 The rights of Liliana Andrade and Frédéric Rousseau to be identified as the authors of this work have been asserted by them in accordance with the Copyright, Designs and Patents Act 1988. Library of Congress Control Number: 2020940076 British Library Cataloguing-in-Publication Data A CIP record for this book is available from the British Library ISBN 978-1-78945-022-4 ERC code: PE6 Computer Science and Informatics PE6_1 Computer architecture, pervasive computing, ubiquitous computing PE6_10 Web and information systems, database systems, information retrieval and digital libraries, data fusion PE7 Systems and Communication Engineering PE7_2 Electrical engineering: power components and/or systems

4 Foreword

5 Acknowledgments

6 PART 1: MPSoC for Telecom PART 1 MPSoC for Telecom 1 From Challenges to Hardware Requirements for Wireless Communications Reaching 6G 1.1. Introduction 1.2. Breadth of workloads 1.3. GFDM algorithm breakdown 1.4. Algorithm precision requirements and considerations 1.5. Implementation 1.6. Conclusion 1.7. Acknowledgments 1.8. References 2 Towards Tbit/s Wireless Communication Baseband Processing: When Shannon meets Moore 2.1. Introduction 2.2. Role of microelectronics 2.3. Towards 1 Tbit/s throughput decoders 2.4. Conclusion 2.5. Acknowledgments 2.6. References

7 PART 2: Application-specific MPSoC Architectures 3 Automation for Industry 4.0 by using Secure LoRaWAN Edge Gateways 3.1. Introduction 3.2. Security in IIoT 3.3. LoRaWAN security in IIoT 3.4. Threat model 3.5. Trusted boot chain with STM32MP1 3.6. LoRaWAN gateway with STM32MP1 3.7. Discussion and future scope 3.8. Acknowledgments 3.9. References 4 Accelerating Virtualized Distributed NVMe Storage in Hardware 4.1. Introduction 4.2. Motivation: NVMe storage for the cloud 4.3. Design 4.4. Implementation 4.5. Results 4.6. Conclusion 4.7. References 5 Modular and Open Platform for Future Automotive Computing Environment 5.1. Introduction 5.2. Outline of this approach 5.3. Results 5.4. Use case 5.5. Conclusion 5.6. References 6 Post-Moore Datacenter Server Architecture 6.1. Introduction 6.2. Background: today’s blades are from the desktops of the 1980s 6.3. Memory-centric server design 6.4. Data management accelerators 6.5. Integrated network controllers 6.6. References

8 PART 3: Architecture Examples and Tools for MPSoC 7 SESAM: A Comprehensive Framework for Cyber–Physical System Prototyping 7.1. Introduction 7.2. An overview of the SESAM platform 7.3. VPSim: fast and easy virtual prototyping 7.4. Hybrid prototyping 7.5. FMI for co-simulation 7.6. Conclusion 7.7. References 8 StaccatoLab: A Programming and Execution Model for Large-scale Dataflow Computing 8.1. Introduction 8.2. Static dataflow 8.3. Dynamic dataflow 8.4. Dataflow execution models 8.5. StaccatoLab 8.6. Large-scale dataflow computing? 8.7. Acknowledgments 8.8. References 9 Smart Cameras and MPSoCs 9.1. Introduction 9.2. Early VLSI video processors 9.3. Video signal processors 9.4. Accelerators 9.5. From VSP to MPSoC 9.6. Graphics processing units 9.7. Neural networks and tensor processing units 9.8. Conclusion 9.9. References 10 Software Compilation and Optimization Techniques for Heterogeneous Multi-core Platforms 10.1. Introduction 10.2. Dataflow modeling 10.3. Source-to-source-based compiler infrastructure 10.4. Software distribution 10.5. Results 10.6. Conclusion 10.7. References

9 List of Authors

10 Author Biographies

11 Index

12 End User License Agreement

1 Chapter 1 Table 1.1. Processing requirement corners as per standard specification Table 1.2. Kernel parameters for corner use cases Table 1.3. Selected GFDM implementation variants Table 1.4. Kernel profile: cycles, memory accesses, and density Table 1.5. GFDM: required frequency budget and performance on our vDSP

2 Chapter 2 Table 2.1. Implementation properties of various coding schemes

3 Chapter 8Table 8.1. A comparison of large FFTs mapped onto a GPU and an FPGATable 8.2. A comparison of the four back-pressure schemes of Figure 8.18Table 8.3. A summary of the StaccatoLab execution model

4 Chapter 10Table 10.1. Retargeting MAPS towards MPSoC platforms

1 Chapter 1Figure 1.1. Application mapping on the rate–latency plane with regard to the rel...Figure 1.2. Comparing 14 OFDM symbols’ TTI duration of 4G and 5GFigure 1.3. Processing load in kRB/s for 5G NR FR1 (Damjancevic et al. 2019)Figure 1.4. Processing load in kRB/s for 5G NR FR2Figure 1.5. Tiled “Kachel” MPSoC with decentralized tightly coupled memoriesFigure 1.6. Heterogeneous MPSoC with a central shared memory architectureFigure 1.7. GFDM processing dataflow diagramFigure 1.8. Visualization of time-domain GFDM filteringFigure 1.9. GFDM pseudo-codeFigure 1.10. Precision test bed set upFigure 1.11. Varied precision quantization of GFDMFigure 1.12. GFDM EVM for varied data and ACC complex bit-lengths compared to ad...Figure 1.13. vDSP simplified HW block diagram

2 Chapter 2Figure 2.1. State-of-the-art commercial system-on-chip baseband architectureFigure 2.2. Left: 306 Gbit/s turbo decoder. Middle: 288 Gbit/s LDPC decoder. Rig...

3 Chapter 3Figure 3.1. Security in LoRaWANFigure 3.2. Boot process in an STM32MP1 deviceFigure 3.3. Execution environments in OP-TEE enabled organization based on ARM T...Figure 3.4. LoraWAN gateway using an RAK831 RF with a GPS (top two shields), the...Figure 3.5. Execution of gateway packet forwarder in OP-TEE enabled organization...

4 Chapter 4Figure 4.1. Hypervisor typesFigure 4.2. Hyperconverged versus disaggregated architecturesFigure 4.3. Comparison of the NexVisor I/O architecture to standard XenFigure 4.4. Optimized I/O datapath operations in the NexVisor for local and remo...Figure 4.5. High-level view of disaggregated storage architecture, showing the I...Figure 4.6. ATA over Ethernet (AoE) header format (Hopkins and Coile 2009)Figure 4.7. Storage virtualization data structures used by the accelerated datap...Figure 4.8. Hardware architecture for the disaggregated storage acceleration car...Figure 4.9. Thousands of sequential read I/Os per second, using fio on four VM c...Figure 4.10. Thousands of sequential write I/Os per second, using fio on four VM...Figure 4.11. Thousands of sequential read I/Os per second, using fio on four VM ...Figure 4.12. AoE read throughput scaling for one to four client flows

5 Chapter 5Figure 5.1. Overall ECU/DCU costs (B$) evolution and breakdown between standard ...Figure 5.2. Overview of the FACE PCU and PIU infrastructureFigure 5.3. Synthetic result of the hardware benchmarkFigure 5.4. Overview of the FACE PCU structureFigure 5.5. Daughterboard physical form factorFigure 5.6. Overview of the FACE PIU structureFigure 5.7. Example of hardware setup of the FACE platform. PCU front and back s...Figure 5.8. Illustration of AUTOSAR adaptive platform software architectureFigure 5.9. ADAS polygraph modelFigure 5.10. The FACE instrumented prototype setupFigure 5.11. Use case interface