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* Corresponding author : tri.suman78@gmail.com

Abhishek Kumar

School of Electronics and Electrical Engineering, Lovely Professional University, Phagwara, India

Abstract

Vedic arithmetic is an old Indian science, discovered from ancient Indian sculptures (Vedas). High-speed more multiple is the primary block in processor architecture. Vedic mathematics developed from a special method of calculations of 16 sutras. This chapter presents VLSI architecture implementation of an 8-bit multiplier with compressors, which shows significant improvement over conventional add shift multiplier. Vedic mathematics developed from 16 principles known as sutras. The technique of Vedic more multiple is Urdhva-Triyakbhyam (Vertically and Crosswise) sutra. This sutra was customarily used in the ancient history of Indian culture to multiply two decimal numbers with minimum time. The hardware architecture of Vedic multiplier is similar to array multiplier. In the performance of digital signal processors which frequently perform multiplication, much depends on the calculation speed of the multiplier block. The existing method of multiplication shift-add, booth multiplication requires hardware resources, which leads to high power consumption. The present method of Vedic multiplication based on the compressor block is focused on the reduction of interconnect wire. The multiplier is implemented using Verilog HDL with cadence NC SIM and the constrain areas, power and delay optimize using underlying block.

Keywords: Vedic multiplier, urdhva-tiryakbhyam, adder, compressor, Hdl, power

High-speed power and low-power multiplication are the fundamental blocks for high-speed processor architecture. It is hard to realize both high-speed and low-power architecture (VLSI tradeoff). There is various multiplier architecture available in the literature. Basically, the multiplier is complete by repeated addition; a full adder is a basic unit of the multiplier, cell area increases proportionally with the number of input increases. Switching power increases with interconnection among the cells. The present work of the Vedic multiplier is focused on reducing the cell count by utilizing a compressor block into the design. The compressor is a combination of multiple adder block. It accepts multiple inputs to perform addition and map the result into a lower number of the output signal.

Vedic arithmetic is derived from Vedas (books of shrewdness) [1]. It is a chunk of Sthapatya-Veda (book on structural building and design), which is an Upaveda (supplement) of Atharva Veda. It incorporated the hypothesis of standard numerical terms having a place in number belonging, geometry (plane, co-ordinate), trigonometry, quadratic conditions, factorization, and even math. His Holiness Jagadguru Shankaracharya Bharati Krishna Teerthaji Maharaja (1884-1960) consolidated his work and introduced it as a scientific clarification. Swamiji consolidated 16 sutras (formulae) and 16 Upa sutras (sub-formulae) from Atharva Veda as shown in Table 2.1. Vedic mathematics consists of the special technique of computations based on natural principles. Mathematical problems in trigonometric, algebra, and geometry can be solved simply. The Vedic method contains 16 sutras, describing natural ways of computing. The beauty of Vedic mathematics is that it simplifies complex calculations. The Vedic method shows effective methods of implementation of multiplication with higher bits for the science and engineering field.

Table 2.1 Sutra in Vedic mathematics [2–5].

Vedic mathematics is one of ancient Indian mathematics computes mathematical operations and is actively based on formulas for fast computations “Urdhva-Tiryakbhyam”. Sutra is more generic and appropriate for multiplication. The meaning of Urdhva-Tiryakbhyam is “vertically and crosswise”. The significant advantage of the Urdhva-Tiryakbhyam multiplication method is that it requires at most logical “AND” operations, arrangements of half adder (HA) and full adder (FA) to accomplish multiplication [6, 7]. Partial products require in multiplication generated in Parallel, minimizes computation time. In Figure 2.1, darkened circles present the bits of “multiplier and multiplicand”; arrows present bits to multiplied compute each bits of product.