Hafiz M. H. Babu - Reversible and DNA Computing

18 Chapter 18Figure 18.1 Adaptive structure of ( n , k ) logarithmic barrel shifter.Figure 18.2 (4, 2) Reversible fault‐tolerant unidirectional logarithmic barr...Figure 18.3 (8, 3) Reversible fault‐tolerant unidirectional logarithmic barr...Figure 18.4 Reversible fault‐tolerant unidirectional logarithmic right rot...Figure 18.5 (4, 2) Reversible fault‐tolerant unidirectional logarithmic logi...Figure 18.6 (8,3) Reversible fault‐tolerant unidirectional logarithmic logic...Figure 18.7 ( n,k ) reversible fault‐tolerant logarithmic logical shifter (cir...

19 Chapter 19Figure 19.1 AND Ex‐OR programmable logic array.Figure 19.2 Four different orientations.Figure 19.3 Realization of multi‐output function (F) based on Algorithm 19.1...Figure 19.4 Realization of multi‐output function based on Algorithm 19.1.1...Figure 19.5 Different representations of Fredkin gate.Figure 19.6 The design of AND plane of reversible fault‐tolerant PAL.Figure 19.7 Feynman extension gate (FEG).Figure 19.8 The design of the Ex‐OR plane of a reversible fault‐tolerant PAL...Figure 19.9 The block diagram of reversible fault‐tolerant MSH gate.Figure 19.10 The quantum realization of reversible fault‐tolerant MSH gate w...Figure 19.11 The block diagram of reversible fault‐tolerant MSB gate.Figure 19.12 The quantum realization of reversible fault‐tolerant MSB gate w...Figure 19.13 The transistor realization of reversible fault‐tolerant MSH gat...Figure 19.14 The transistor realization of reversible fault‐tolerant MSB gat...Figure 19.15 The block diagram of reversible fault‐tolerant D latch.Figure 19.16 The block diagram of reversible fault‐tolerant master–slave fli...Figure 19.17 The block diagram of a reversible fault–tolerant 4 1 multiple...Figure 19.18 The block diagram of reversible fault‐tolerant three‐input LUT....Figure 19.19 The block diagram of reversible fault‐tolerant four‐input LUT....Figure 19.20 The block diagram of reversible fault‐tolerant CLB of FPGA.

20 Chapter 20Figure 20.1 Reversible fault‐tolerant UPPG gate.Figure 20.2 Quantum realization of LMH gate.Figure 20.3 Circuit structure of Group‐1 PP cell.Figure 20.4 Compressed block diagram of Group‐1 PP cell.Figure 20.5 Block diagram of Group‐2 PP (Cell) .Figure 20.6 Block diagram of Group‐2 PP cell.Figure 20.7 Block diagram of Group‐3 PP cell.Figure 20.8 Reversible fault‐tolerant 2‐bit ALU.Figure 20.9 n ‐bit reversible fault‐tolerant ALU.

21 Chapter 21Figure 21.1 Reversible logic gate R1.Figure 21.2 Reversible logic gate R2.Figure 21.3 Reversible logic gate R3.Figure 21.4 Realizations of OR and Ex‐OR Gates Using R1 Gate.Figure 21.5 Realizations of Ex‐NOR and NAND gates using R1 gate.Figure 21.6 Realization of NOR gate using R1 gate.Figure 21.7 Realization of AND gate using R1 gate.Figure 21.8 The testable logic block using R1 and R2 gates.Figure 21.9 Two‐pair rail checker.Figure 21.10 Testable block embedded with two‐pair rail checker.Figure 21.11 Realization of NAND gate using R1 and R2 gates.Figure 21.12 Reversible NAND block implementation for the function ab + cd ...Figure 21.13 Implementation of signal duplication.

22 Chapter 22Figure 22.1 Block diagram of R1 gate.Figure 22.2 Block diagram of R2 gate.Figure 22.3 Block diagram of R gate.Figure 22.4 Construction of a testable block (TB).Figure 22.5 Block diagram of a testable block (TB).Figure 22.6 Block diagram of UFT gate.Figure 22.7 Compact representation of a UFT gate.Figure 22.8 Quantum realization of a UFT circuit.Figure 22.9 AND and EX‐OR operations of UFT gate.Figure 22.10 OR operation of UFT gate.Figure 22.11 NAND and NOT operations of UFT gate.Figure 22.12 EX‐OR and EX‐NOR operations of UFT gate.Figure 22.13 NOR operation of the UFT gate.Figure 22.14 Nontestable circuit for .Figure 22.15 Online testable circuit for Example 22.2.2.1.Figure 22.16 Nontestable full adder using ESOP technique.Figure 22.17 Online testable full adder circuit.

23 Chapter 23Figure 23.1 Reversible computer dissipates less heat than a conventional com...Figure 23.2 Reversible computer has the same number of outputs and inputs.Figure 23.3 Working mechanism of a reversible computer.Figure 23.4 Reversible logic gates.Figure 23.5 Back‐up states of a reversible computing system.

24 Chapter 24Figure 24.1 Hydrogen bonds of the interior DNA.Figure 24.2 DNA structureFigure 24.3 Structure of DNA.Figure 24.4 Ligation process of DNA.Figure 24.5 HPP on seven vertices.Figure 24.6 DNA replication process.

25 Chapter 25Figure 25.1 Overview of the methodology.Figure 25.2 Part of the tree structure.Figure 25.3 Structure of a node.Figure 25.4 DNA sequence of a node for 20 nodes tree.Figure 25.5 DNA combination.

26 Chapter 26Figure 26.1 Operation of DNA‐based reversible NOT gate (DRNG).Figure 26.2 Operation of DNA‐based reversible Ex‐OR gate.Figure 26.3 Operation of DNA‐based reversible AND gate.Figure 26.4 Operation of DNA‐based reversible OR gate.Figure 26.5 Overall procedures of DNA hybridization for a DNA‐based Toffoli ...Figure 26.6 DNA‐based Toffoli gate as NOT gate.Figure 26.7 DNA‐based Toffoli gate as AND gate.Figure 26.8 DNA‐based Toffoli gate as OR gate.Figure 26.9 DNA‐based Toffoli gate as Ex‐OR gate.Figure 26.10 Procedures of DNA hybridization for DNA‐based Fredkin gate.Figure 26.11 DNA hybridization of selection operation between two ANDed prod...Figure 26.12 Gate‐level representation of reversible half‐adder using Toffol...Figure 26.13 Reversible DNA‐based half‐adder.

27 Chapter 27Figure 27.1 Gate‐level representation of a reversible full‐adder circuit.Figure 27.2 Operation of DNA‐based reversible full‐adder circuit.Figure 27.3 DNA‐based reversible adder/subtractor circuit.Figure 27.4 DNA hybridization of logical AND operation using DNA‐based Toffo...Figure 27.5 DNA hybridization of logical NOT operation using DNA‐based Toffo...Figure 27.6 DNA hybridization of logical AND operation between complemented ...Figure 27.7 DNA hybridization of logical Ex‐OR operation using DNA‐based Tof...Figure 27.8 DNA hybridization of selection operation using DNA‐based Fredkin...Figure 27.9 The working principle of DNA comparator.

28 Chapter 28Figure 28.1 Operation of DNA‐based reversible NOT gate.Figure 28.2 The four basic biochemical events of the shifter circuit.Figure 28.3 The working procedures of DNA‐based reversible multiplication op...Figure 28.4 An example of DNA‐based reversible multiplication operation.

29 Chapter 29Figure 29.1 Block diagram of DNA‐based reversible multiplexer circuit.Figure 29.2 DNA hybridization of the first Fredkin gate for selection operat...Figure 29.3 DNA hybridization of second Fredkin gate for selection operation...Figure 29.4 DNA hybridization of third Fredkin gate for selection operation....Figure 29.5 DNA hybridization of the fourth Fredkin gate for selection opera...Figure 29.6 DNA hybridization of the fifth Fredkin gate for selection operat...Figure 29.7 Diagram of DNA‐based reversible logic unit.Figure 29.8 Diagram of DNA‐based reversible logic unit.