Hafiz M. H. Babu - Reversible and DNA Computing

4 Chapter 4Figure 4.1 Two‐input n ‐bit reversible MUX.Figure 4.2 A clocked D Flip‐Flop.Figure 4.3 An n ‐bit reversible D flop‐flop.Figure 4.4 Implementation of the characteristic function of Equation (4.2.3....Figure 4.5 The structure of the basic cell for the reversible PIPO left‐shif...Figure 4.6 The block diagram of the basic cell for the reversible PIPO left‐...Figure 4.7 An n ‐bit reversible PIPO left‐shift register.Figure 4.8 An ‐bit parallel adder (carry‐out ignored).Figure 4.9 Illustration of the division circuit.

5 Chapter 5Figure 5.1 Reversible BJS gate.Figure 5.2 Quantum realization of the BJS gate.Figure 5.3 Reversible HLN gate.Figure 5.4 Quantum realization of the HLN gate.Figure 5.5 BJS gate works as reversible 1‐bit comparator.Figure 5.6 BJS gate works as reversible MSB comparator.Figure 5.7 The GE comparator cell.Figure 5.8 Block diagram of the single‐bit GE comparator cell.Figure 5.9 The LT comparator cell.Figure 5.10 Block diagram of the single‐bit LT comparator cell.Figure 5.11 Reversible 2‐bit comparator.Figure 5.12 Reversible n ‐bit comparator.

6 Chapter 6Figure 6.1 Mapping of JK latch (Equation ) on the Fredkin gate.Figure 6.2 Mapping of variable (Equation J ) on the Fredkin gate.Figure 6.3 Reversible design of latch with minimal garbage outputs.Figure 6.4 Conventional cross‐coupled SR latch.Figure 6.5 Peres gate based SR latch without enable.Figure 6.6 Reversible SR latch based on modified truth table.Figure 6.7 Reversible gated SR latch based on modified truth table.Figure 6.8 Fredkin gate‐based D latch with one Feynman gate.Figure 6.9 Fredkin gate‐based D latch with two Feynman gates.Figure 6.10 Fredkin gate‐based negative enable reversible D latch with only ...Figure 6.11 Fredkin gate‐based negative enable reversible D latch with outpu...Figure 6.12 Peres gate‐based latch.Figure 6.13 Reversible T latch with outputs and .Figure 6.14 Reversible JK latch with outputs and .Figure 6.15 Reversible master–slave D flip‐flop.Figure 6.16 Reversible master–slave T flip‐flop.Figure 6.17 Reversible master–slave JK flip‐flop.Figure 6.18 Reversible master–slave SR flip‐flop.Figure 6.19 Application of the Fredkin gate to avoid the fan‐out.Figure 6.20 Asynchronous reset of the and outputs of the Fredkin gate.Figure 6.21 Asynchronous set of the and outputs of the Fredkin gate.Figure 6.22 Fredkin gate‐based asynchronous set/reset D latch.Figure 6.23 Reversible asynchronous set/reset master–slave D flip‐flop.

7 Chapter 7Figure 7.1 Reversible flip‐flop.Figure 7.2 Reversible clocked T flip‐flop for synchronous counter.Figure 7.3 Reversible clocked T flip‐flop for asynchronous counter.Figure 7.4 Block diagram of MPG gate.Figure 7.5 Quantum representation of 3 3 MPG gate.Figure 7.6 Reversible master–slave T flip‐flop.Figure 7.7 4‐bit reversible asynchronous counter.Figure 7.8 4‐bit reversible synchronous counter.Figure 7.9 Quantum implementation of a reversible 2– to –4 decoder.Figure 7.10 Measurement of the quantum delay for the reversible 2– to –4 decod...Figure 7.11 Reversible 2– to –4 decoder.Figure 7.12 Reversible 4–to–2 encoder.

8 Chapter 8Figure 8.1 Simple block diagram of the barrel shifter.Figure 8.2 Block diagram of the reversible MBJN gate.Figure 8.3 Quantum realization of the reversible MBJN gate.Figure 8.4 Reversible 2‐bit 2's complement generator.Figure 8.5 Reversible 3‐bit 2's complement generator.Figure 8.6 Reversible 3‐bit swap condition generator.Figure 8.7 Reversible 4‐bit swap condition generator.Figure 8.8 A (4, 3) reversible right rotator.Figure 8.9 Block diagram of (8, 7) reversible bidirectional barrel shifter....Figure 8.10 Structure of the reversible clocked D flip‐flop.Figure 8.11 Block diagram of the reversible clocked D flip‐flop.Figure 8.12 n ‐bit reversible SISO shift register.Figure 8.13 n ‐bit reversible SIPO shift register.Figure 8.14 n ‐bit reversible PISO shift register.Figure 8.15 Implementation of the characteristic function of Equation (8.2.1...Figure 8.16 Basic cell for the reversible PIPO shift register.Figure 8.17 Block diagram for the reversible PIPO shift register.Figure 8.18 n ‐bit reversible PIPO shift register.Figure 8.19 Implementation of the characteristic function of Equation (8.2.1...Figure 8.20 Basic cell for the reversible universal shift register.Figure 8.21 Block diagram for the reversible universal shift register.Figure 8.22 n ‐bit reversible universal shift register.

9 Chapter 9Figure 9.1 Reversible gate 1 (RG1).Figure 9.2 Reversible gate 2 (RG2).Figure 9.3 Reversible R‐I gate.Figure 9.4 Transistor level realization of reversible R‐I gate.Figure 9.5 Realization of 2:1 multiplexer using reversible R‐I gate.Figure 9.6 Realization of 1:2 demultiplexer using reversible R‐I gate.Figure 9.7 Realization of two‐input XOR using reversible R‐I gate.Figure 9.8 Realization of two‐input AND gate using reversible R‐I gate.Figure 9.9 Reversible R‐II gate.Figure 9.10 Transistor level circuit for the reversible R‐II gate.Figure 9.11 Realization of 2:1 multiplexer using reversible R‐II gate.Figure 9.12 Realization of two‐input XOR and half adder using reversible R‐I...Figure 9.13 Realization of two‐input AND gate using reversible R‐II gate.

10 Chapter 10Figure 10.1 Block diagram of 3 3 reversible NH gate.Figure 10.2 Quantum realization of 3 3 reversible NH gate.Figure 10.3 Block diagram of 4 4 reversible BSP gate.Figure 10.4 4‐to‐1 reversible MUX.Figure 10.5 Reversible D latch.Figure 10.6 Reversible Write‐Enabled Master–Slave flip‐flop.Figure 10.7 Block diagram of a reversible RAM.Figure 10.8 A reversible logic element of Plessey FPGA.Figure 10.9 Reversible MUX gate.Figure 10.10 Different uses of a Feynman gate.Figure 10.11 One template of toffoli gate.Figure 10.12 Two templates of MUX gate.Figure 10.13 Ex‐OR plane realization for the function F based on the Algorit...Figure 10.14 Design of reversible PLAs for multi‐output function F .Figure 10.15 Delay calculation of AND plane: (a‐b) delay propagation path of...Figure 10.16 Delay calculation of Ex‐OR plane: (a‐b) delay propagation path ...