Hafiz M. H. Babu - Reversible and DNA Computing

11 Chapter 11Figure 11.1 Block diagram of reversible FS gate.Figure 11.2 Quantum realization of reversible FS gate.Figure 11.3 Reversible decoder.Figure 11.4 3 2 Reversible decoder.Figure 11.5 n reversible decoder.Figure 11.6 Reversible D flip‐flop.Figure 11.7 Reversible write‐enabled master–slave D flip flop.Figure 11.8 Reversible RAM.Figure 11.9 Reversible ITS decoder.Figure 11.10 Quantum representation of reversible ITS decoder.Figure 11.11 Block diagram of reversible PROM.Figure 11.12 Reversible TI gate.Figure 11.13 Different uses of Feynman gate.Figure 11.14 Template of Toffoli gate.Figure 11.15 Two templates of TI gate.Figure 11.16 The combined design of AND plane and Ex‐OR plane.

12 Chapter 12Figure 12.1 Logic diagram of a conventional ALU.Figure 12.2 The reversible function generator.Figure 12.3 Block diagram of reversible function generator.Figure 12.4 The reversible control unit.Figure 12.5 Block diagram of the reversible control unit.Figure 12.6 The design of 16‐bit reversible ALU.

13 Chapter 13Figure 13.1 Block diagram of a 16‐bit control unit.Figure 13.2 Block diagram of reversible HL gate.Figure 13.3 Quantum realization of reversible HL gate.Figure 13.4 Block diagram of reversible BJ gate.Figure 13.5 NAND implementation of reversible BJ gate.Figure 13.6 2‐to‐4 Reversible decoder using FG and FRG gate.Figure 13.7 2‐to‐4 Reversible decoder using HL gate.Figure 13.8 Reversible 3‐to‐8 decoder (Approach 1).Figure 13.9 Reversible 3‐to‐8 decoder (Approach 2).Figure 13.10 Reversible ‐to‐ decoder (Approach 1).Figure 13.11 Reversible ‐to‐ decoder (Approach 2).Figure 13.12 Reversible JK flip flop.Figure 13.13 4‐bit reversible sequence counter.Figure 13.14 16‐bit reversible instruction register.Figure 13.15 Reversible control gates associated with AR.

14 Chapter 14Figure 14.1 Feynman double gate.Figure 14.2 Feynman double gate preserves fault tolerance over input–output ...Figure 14.3 Fredkin gate.Figure 14.4 New fault‐tolerant gate.Figure 14.5 Parity‐preserving HC gate.Figure 14.6 Parity‐preserving IG gate.Figure 14.7 Parity‐preserving IG gate as a NOT gate.Figure 14.8 Parity‐preserving IG gate as AND gate and Ex‐OR gate.Figure 14.9 Parity‐preserving IG gate as Ex‐OR gate, Ex‐NOR gate and OR gate...Figure 14.10 Quantum representation of NFT gate.Figure 14.11 Design of single NFT full adder.Figure 14.12 Design of fault‐tolerant CSA.Figure 14.13 Design of 4‐bit fault‐tolerant CLA.Figure 14.14 FTFA circuit.Figure 14.15 Fault‐tolerant ripple carry adder.

15 Chapter 15Figure 15.1 Working procedure of a multiplier circuit.Figure 15.2 Reversible LMH gate.Figure 15.3 Quantum realization of LMH gate.Figure 15.4 Partial product generator circuit.Figure 15.5 Generalized architecture of fault‐tolerant PPG.Figure 15.6 multi‐operand addition circuit.Figure 15.7 Generalized architecture of fault‐tolerant MOA.

16 Chapter 16Figure 16.1 Illustration of the decomposition of a binary number.Figure 16.2 Example of a division operation.Figure 16.3 2‐input ‐bit reversible fault‐tolerant MUX.Figure 16.4 Block diagram of RR gate.Figure 16.5 Reversible fault‐tolerant D latch using RR gate.Figure 16.6 Block diagram of F2PG gate.Figure 16.7 Reversible fault‐tolerant PIPO left‐shift register.Figure 16.8 Reversible fault‐tolerant register.Figure 16.9 Reversible fault‐tolerant rounding register.Figure 16.10 Reversible fault‐tolerant normalization register.Figure 16.11 Reversible fault‐tolerant NFTFAG.Figure 16.12 Quantum representation of NFTFAG.Figure 16.13 NFTFAG as a reversible fault‐tolerant full adder.Figure 16.14 ‐bit reversible fault‐tolerant parallel adder.Figure 16.15 ‐bit reversible fault‐tolerant parallel adder.Figure 16.16 Block diagram of the 2‐bit reversible fault‐tolerant division c...

17 Chapter 17Figure 17.1 Block diagram of F2G.Figure 17.2 Quantum equivalent realization of F2G.Figure 17.3 Transistor realization of F2G.Figure 17.4 Block diagram of FRG.Figure 17.5 Quantum equivalent realization of FRG.Figure 17.6 Transistor realization of FRG.Figure 17.7 ‐to‐ Reversible fault‐tolerant decoder.Figure 17.8 Block diagram of the ‐to‐ RFD.Figure 17.9 Block diagram of the ‐to‐ RFD.Figure 17.10 Schematic diagram of the ‐to‐ RFD.Figure 17.11 Block diagram of the ‐to‐ decoder.Figure 17.12 Combinations of the two quantum primitive gates.