Philippe Darche - Microprocessor 4

1 Cover

2 Title page Series EditorJean-Charles Pomerol

3 Copyright First published 2020 in Great Britain and the United States by ISTE Ltd and John Wiley & Sons, Inc. Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address: ISTE Ltd 27-37 St George’s Road London SW19 4EU UK www.iste.co.uk John Wiley & Sons, Inc. 111 River Street Hoboken, NJ 07030 USA www.wiley.com © ISTE Ltd 2020 The rights of Philippe Darche to be identified as the author of this work have been asserted by him in accordance with the Copyright, Designs and Patents Act 1988. Library of Congress Control Number: 2020943937 British Library Cataloguing-in-Publication Data A CIP record for this book is available from the British Library ISBN 978-1-78630-566-4

4 Quotation

5 Preface

6 Introduction

7 1 Coding and Addressing Modes 1.1. Encoding and formatting an instruction 1.2. Addressing modes 1.3. Conclusion

8 2 Instruction Set and Class 2.1. Definitions 2.2. Transfer instructions 2.3. Data processing instructions 2.4. Control transfer instructions 2.5. Environmental instructions 2.6. Parallelism instructions 2.7. Extensions to instruction sets 2.8. Various instructions 2.9. Conclusion

9 3 Additional Concepts 3.1. Concepts associated with the instruction set and programming 3.2. Concepts linked to execution 3.3. Hardware and software compatibilities 3.4. Measuring processor performances 3.5. Criteria for choosing 3.6. Conclusion

10 4 Subroutine 4.1. Stack memory 4.2. Subroutine 4.3. Conclusion

11 5 Interrupt Mechanism 5.1. Origin, definition and classification 5.2. External causes 5.3. Nested interrupts 5.4. Internal causes 5.5. Debugging 5.6. Priority between internal and external interrupts 5.7. Identification of the source and vectorization 5.8. Nested and queued interrupts 5.9. Uses 5.10. Interrupts and execution modes 5.11. Interrupts and advanced architectures 5.12. Conclusion

12 Conclusion of Volume 4

13 Exercises

14 Appendix

15 Acronyms

16 References

17 Index

18 End User License Agreement

1 Chapter 1Figure 1.1. Breakdown of an instruction Figure 1.2. An example of the structure of an operation code Figure 1.3. Format of an instruction with two operands Figure 1.4. An instruction with several operands Figure 1.5. Three fixed formats for MIPS instructions Figure 1.6. Typical instruction format from 8086/88 Figure 1.7. Variable instruction format Intel IA-32 and Intel 64 (Intel 2016) ar...Figure 1.8. Instruction with an operand field Figure 1.9. Execution of an instruction using register addressing from one regis...Figure 1.10. Instruction with direct addressing Figure 1.11. Instruction with an address at page 0 Figure 1.12. Execution of an instruction in relative addressing Figure 1.13. Seeking an operand in relative addressing Figure 1.14. Instruction with indirect register addressing Figure 1.15. Instruction with indirect memory addressing Figure 1.16. Execution of an instruction in indexed addressing with displacement...Figure 1.17. Execution of an instruction in indexed addressing with displacement...Figure 1.18. Execution of an instruction in base addressing with displacement Figure 1.19. Indirect indexed addressing or pre-indexing Figure 1.20. Indirect indexed addressing or post-indexing Figure 1.21. Indirect indexed zero-page addressing of MCS6502 Figure 1.22. Execution of an instruction in bit addressing Figure 1.23. Window of five samples Figure 1.24. Circular buffer Figure 1.25. Comparison between linear and circular addressings (from Rao (2001)...Figure 1.26. Flow diagram of the algorithm of an 8-point FFT DIT in base 2

2 Chapter 2Figure 2.1a. Instruction classification in modern MPUs Figure 2.1b. Classifying instructions in modern MPUs (continuation and end) Figure 2.2a. Classification of the main bit manipulation operations Figure 2.2b. Classification of the main bit manipulation operations (continuatio...Figure 2.3. Logical left and right shifts Figure 2.4. Shift arithmetic right Figure 2.5. Left and right rotations Figure 2.6. Left and right rotations through carry Figure 2.7. Generic examples of multiple shifts and rotation Figure 2.8. Double shift with a 386 Figure 2.9. Field extract and field deposit operations Figure 2.10. Left shuffle operation (interleaving) Figure 2.11. Right shuffle operation (interleaving) Figure 2.12. Reverse instructions from the Arm® and Thumb® family (n = 64) Figure 2.13. Classifying advanced bit manipulations Figure 2.14. Field extract and field deposit operations of parallel bits Figure 2.15. Normal butterfly circuit in n = 8 bits format (a) and associated sw...Figure 2.16. Reverse butterfly circuit in n = 8 bits format Figure 2.17. Branching instructions Figure 2.18. Execution paths for a jump Figure 2.19. Execution steps for a conditional jump Figure 2.20. Execution paths for a conditional jump Figure 2.21. Left: result state check; right: direct check Figure 2.22. Schema for evaluating a calculation Figure 2.23. Condition field from MPU Arm® VL86C010 Figure 2.24. Instruction buffer Figure 2.25. Hardware management of a loop Figure 2.26. Functional block diagram showing a hardware loop manager (from Tsao...Figure 2.27. Distribution of operations in a vector instruction in a SIMD struct...

3 Chapter 3Figure 3.1. Instruction alignment in 32-bit format (from Darche (2012) modified) Figure 3.2. Levels of programming language Figure 3.3. Hierarchy of protected execution modes from the x86 family from Inte...Figure 3.4. Operating modes of an MPU from IA-323 architecture from Intel® (Inte...Figure 3.5. Virtualization in an application Figure 3.6. Hypervision of virtual machines Figure 3.7. Differences between container (a) and serverless (b) (from Wong (201...Figure 3.8. Hierarchization of the instruction set from x86 architecture Figure 3.9. Backward compatibility of the instruction set architecture by enrich...Figure 3.10. Types of compatibility of a digital system Figure 3.11. Evolution of the calculating performance (MIPS) of the first MPUs f...Figure 3.12. Development of MPU systems’ performance over time (SPECint) Figure 3.13. Comparison of uniprocessor performances between supercomputers and ...Figure 3.14. Comparing (single-core) MPU performances with DRAM8 performances (f...Figure 3.15. Comparison of performances between computer classes (from Hennessy ...

4 Chapter 4Figure 4.1. Suggested visual representation of a stack S Figure 4.2. Pseudo-code for stacking (a) and unstacking (b) in the format n = 16...Figure 4.3. Operations of stacking and unstacking for TMS320C31 Figure 4.4. Managing an ascending stack Figure 4.5. Classical structure of an execution stack (x86 family from Intel) Figure 4.6. Classic main memory mapping Figure 4.7. Stack register of a mathematical coprocessor in floating point from ...Figure 4.8. Stack in shift-register version Figure 4.9. Unfolding execution of a program with a call to sub-program Figure 4.10. Subroutine call and return and stack content (x86 architecture) Figure 4.11. Recursive calls and returns from a subroutine (nested calls) Figure 4.12. Recursive calls and returns from a subroutine (nested calls) Figure 4.13. Windowing registers (from Scott (2016))