Philippe Darche - Microprocessor 4

5 Chapter 5Figure 5.1. Origins of an interrupt request (Darche 2003) Figure 5.2. Ideal forms of external interrupt request Figure 5.3. Call and return of a non-nested hardware interrupt Figure 5.4. Execution flow of a program during a hardware interrupt request Figure 5.5. Stages in handling an interrupt Figure 5.6. Different sources of external interrupts Figure 5.7. Example of management logic for IT requests (Meinadier 1971, 1988) Figure 5.8. Processing chain for several sources of interrupt sharing a single i...Figure 5.9. Simplified decision organigram for considering a hardware interrupt Figure 5.10. Execution organigram of a simple MPU: the MC6802 (Motorola 1984) Figure 5.11. Pre-emptive execution in a system of hierarchized interrupts Figure 5.12. Simplified processing logigram of an interrupt from the IT 8259A co...Figure 5.13. Mechanism of nested hardware interrupts Figure 5.14. Call and return of a non-nested software interrupt (example with MC...Figure 5.15. Call and return of nested software interrupts (example with MC6809) Figure 5.16. Call and return of nested software interrupts (example with MC6809) Figure 5.17. Decision process from MC6809 (simplified organigram without HALT an...Figure 5.18. Processing sequence for interrupt requests from 8086 (Intel 1989) Figure 5.19. Step-by-step execution modes with NMI and normal (Intel 1989) Figure 5.20. Simultaneous software exception and maskable external interrupt int...Figure 5.21. Simultaneous NMI, INTR and division by zero in interaction with ste...Figure 5.22. Processing organigram for interrupts from MC6809 (Motorola 1981, 19...Figure 5.23. Vectorization of the interrupt Figure 5.24. External vectorization Figure 5.25. Two typical implantations of different memory areas of an IT system Figure 5.26. Proposal for processing flow for many IT requests (Intel 1980) Figure 5.27. Organization of different APICs

6 ExercisesFigure E2.28. Generation of address signals corresponding to an execution of a s...

1 Chapter 1Table 1.1. Possible address combinations in family IA-32 Table 1.2. Combined MC6809 addressing modes

2 Chapter 2Table 2.1. Logical instructions from DEC System-10 Table 2.2. Conditional jump instructions for 8086 for whole numbers Table 2.3. Condition codes from the Arm® architecture

3 Chapter 3Table 3.1. Additional cost in the number of cycles and memory clutter for the MC...Table 3.2. Effective address calculation time (8086) Table 3.3. Arm® architecture execution modes Table 3.4. List of iCOMP benchmarks

4 Chapter 4Table 4.1. Solutions for managing a stack in main memory

5 Chapter 5Table 5.1. Maskable and non-maskable interrupts Table 5.2. Categories of interrupt to qualify a double fault in 80386 (Intel 198...Table 5.3. Decision criteria for qualifying a double fault in 80386 (Intel 1986) Table 5.4. Priorities of different interrupts from 8086 Table 5.5. Table of 256 interrupt vectors from IA-32 architecture Table 5.6. List of exception codes (ExcCode) for MIPS architecture (Kane 1988; K...Table 5.7. Management options in the case of multiple IT processing Table 5.8. Table summarizing interrupts Table 5.9. Interrupt recovery points for the 80286 Table 5.10. Recovery point for ITs for the 80286 (real mode) Table 5.11. Recovery point for ITs for the 80286 (protected mode) Table 5.12a. Suggestion for classification criteria according to Hennessy and Pa...Table 5.12b. Suggestion of classification criteria according to Hennessy and Pat...

6 AppendixTable A.1a. Hexadecimal values of machine codes Table A.1b. Hexadecimal values of machine codes Table A.2a. Programming aid Table A.2b. Programming aid Table A.2c. Programming aid

1 Cover

2 Table of Contents

3 Title page Series EditorJean-Charles Pomerol

4 Copyright First published 2020 in Great Britain and the United States by ISTE Ltd and John Wiley & Sons, Inc. Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address: ISTE Ltd 27-37 St George’s Road London SW19 4EU UK www.iste.co.uk John Wiley & Sons, Inc. 111 River Street Hoboken, NJ 07030 USA www.wiley.com © ISTE Ltd 2020 The rights of Philippe Darche to be identified as the author of this work have been asserted by him in accordance with the Copyright, Designs and Patents Act 1988. Library of Congress Control Number: 2020943937 British Library Cataloguing-in-Publication Data A CIP record for this book is available from the British Library ISBN 978-1-78630-566-4

5 Quotation

6 Preface

7 Introduction

8 Begin Reading

9 Conclusion of Volume 4

10 Exercises

11 Appendix

12 Acronyms

13 References

14 Index

15 End User License Agreement

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