Design and Development of Efficient Energy Systems

16-bit multiplier needs 666 cells to implement. Here unwanted sub-threshold current which is leakage of power in 60576.57 nW. The dynamic power of 16-bit multiplier to complete product are 444556.31 nW and the total power obtained to 505132.87 nW as shown in Table 2.7.

Table 2.6 Cell area of 16x16 vedic multiplier.

Table 2.7 Power constraints of 16x16 vedic multiplier.

Table 2.8 Time constraint of 16x16 vedic multiplier.

Table 2.9 Comparison of multiplier architecture.

Here pin p[30] defines that it is the last output pin of 16x16 Vedic Multiplier and type defines whether it is input port or output port. The longest path arrival time form input to pin p[30] is 5476 ps shown in Table 2.8.

The present work of 8-bit Vedic multiplier is compared with the existing different architecture of multiplier, shown in Table 2.9in terms of power, delay and cell area. It is observed that the Dadda multiplier needs a large number of nets that require a lower area than the Wallace tree multiplier. Booth requires a lower number of cells but the total area increases to approximately three- to four-fold compare to the Wallace tree and Dadda multiplier [17–19]. Since the booth multiplication algorithm requires multiple time shifting-adding greater number of wire resources.

Vedic multiplier replaces the underlying cell by compressors logic, made up of adder block. Utilization of compressor greatly reduces the wiring resource save area. The leakage power of the Vedic multiplier is larger than other compare multipliers but shows very low dynamic power consumption. Dadda multiplier requires maximum power to reduce the delay 2.56ns. A Vedic multiplier attains significant reduction in dynamic power requirement and delay of multiplication architecture. Cell count of VM is 139 which is much smaller than other multipliers.

The present work Vedic multiplier finds application to implement the architecture of the following [21–25]

1 1) High-speed signal processing

2 2) DSP based application

3 3) DWT and DCT transformation

4 4) FIT and IIR filter

5 5) Multirate signal processing

6 6) Up-Down converters

7 7) Multiply - Accumulate unit

An efficient productive strategy for multiplication based on Urdhva Tiryakbhyam Sutra (Algorithm) in view of Vedic mathematics is implemented in this paper with Verilog HDL. Here a fast 8-bit multiplier is implemented that incorporates architecture of compressor. Compressor is a derived structure of full adder and half adder, map multiple input to lesser number of output signals. Hierarchical multiplier structure and shows the computational speed by offered by Vedic methods. Essential inspiration of this work is to decrease the delay in complex multiplication achieve 2.637 ns. We can deduce that the compressor-based architecture of Vedic math’s multiplier is more favorable than conventional multipliers and preferred in complex algorithm implementation. Hence, we have concluded that Instance Power usage of 8x8 Vedic Multiplier is 40.48% and 16x16 Vedic Multiplier is 62.22%. The Net Power usage of 8x8 Vedic Multiplier is 82.24%, and the 16x16 Vedic Multiplier is 86.85%.

1. Thapliyal, H., & Arabnia, H. R. (2004, June). A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics. In ESA/VLS , 2004I (pp. 434-439).

2. Ciminiera, L., & Valenzano, A. (1988). Low-cost serial multipliers for high-speed specialized processors. The Proceedings IEEE (Computers and Digital Techniques), 135(5), 259-265.

3. Hsiao, S. F., Jiang, M. R., & Yeh, J. S. (1998). Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers. Electronics Letters , 34(4), 341-343.

4.. Ramalatha, M., Dayalan, K. D., Dharani, P., & Priya, S. D. (2009, July). High-speed energy efficient ALU design using Vedic multiplication techniques. In International Conference on Advances in Computational Tools for Engineering Applications , 2009, IEEE (pp. 600-603).

5. Tiwari, H. D., Gankhuyag, G., Kim, C. M., & Cho, Y. B. (2008, November). Multiplier design based on ancient Indian Vedic Mathematics. In International SoC Design Conference, 2008, IEEE (Vol. 2, pp. II-65).

6. Ma, W., & Li, S. (2008, October). A new high compression compressor for large multiplier. In 9th International Conference on Solid-State and Integrated-Circuit Technology. 2008 , IEEE (pp. 1877-1880).

7. Chandrakasan, A. P., Bowhill, W. J., & Fox, F. (2000). Design of high-performance microprocessor circuits. Wiley-IEEE Press.

8. Radhakrishnan, D., & Preethy, A. P. (2000, August). Low power CMOS pass logic 4-2 compressor for high-speed multiplication. In Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat. No. CH37144). 2000 , IEEE (Vol. 3, pp. 1296-1298).

9. Mutoh, S. I., Douseki, T., Matsuya, Y., Aoki, T., Shigematsu, S., & Yamada, J. (1995). 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS. IEEE Journal of Solid-state Circuits , 30(8), 847-854.

10. Sriraman, L., & Prabakar, T. N. (2012, March). Design and implementation of two variable multiplier using KCM and Vedic mathematics. In 1st International Conference on Recent Advances in Information Technology (RAIT). 2012 , IEEEE (pp. 782-787).

11. Tiwari, H. D., Gankhuyag, G., Kim, C. M., & Cho, Y. B. (2008, November). Multiplier design based on ancient Indian Vedic Mathematics. In International SoC Design Conference. 2008 , IEEE (Vol. 2, pp. II-65).

12. Dandapat, A., Ghosal, S., Sarkar, P., & Mukhopadhyay, D. (2010). A 1.2-ns16× 16-bit binary multiplier using high speed compressors. International Journal of Electrical and Electronics Engineering , 4(3), 234-239.

13. Swee, K. L. S., & Hiung, L. H. (2012, June). Performance comparison review of 32-bit multiplier designs. In 4th International Conference on Intelligent and Advanced Systems (ICIAS2012). 2012, IEEE (Vol. 2, pp. 836-841).