Suman Lata Tripathi - Digital VLSI Design and Simulation with Verilog

Dr. Suman Lata Tripathi

Lovely Professional University, Phagwara, Punjab, India

Dr. Sobhit Saxena

Lovely Professional University, Phagwara, Punjab, India

Dr. Sanjeet Kumar Sinha

Lovely Professional University, Phagwara, Punjab, India

Dr. Govind Singh Patel

IIMT College of Engineering, Greater Noida, UP, India

This edition first published 2022

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Library of Congress Cataloging-in-Publication Data

Names: Tripathi, Suman Lata, author. | Saxena, Sobhit, author. | Sinha, Sanjeet Kumar, author. | Patel, Govind Singh, author.

Title: Digital VLSI design and simulation with Verilog / Suman Lata Tripathi, Sobhit Saxena, Sanjeet Kumar Sinha, Govind Singh Patel.

Description: Hoboken, NJ : John Wiley & Sons, 2022. | Includes bibliographical references and index.

Identifiers: LCCN 2021020790 (print) | LCCN 2021020791 (ebook) | ISBN 9781119778042 (hardback) | ISBN 9781119778066 (pdf) | ISBN 9781119778080 (epub) | ISBN 9781119778097 (ebook)

Subjects: LCSH: Integrated circuits--Very large scale integration--Design and construction. | Verilog (Computer hardware description language)

Classification: LCC TK7874.75 .T75 2022 (print) | LCC TK7874.75 (ebook) | DDC 621.39/5028553--dc23

LC record available at https://lccn.loc.gov/2021020790LC ebook record available at https://lccn.loc.gov/2021020791

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1 Cover

2 Title page Digital VLSI Design and Simulation with Verilog Dr. Suman Lata Tripathi Lovely Professional University, Phagwara, Punjab, India Dr. Sobhit Saxena Lovely Professional University, Phagwara, Punjab, India Dr. Sanjeet Kumar Sinha Lovely Professional University, Phagwara, Punjab, India Dr. Govind Singh Patel IIMT College of Engineering, Greater Noida, UP, India

3 Copyright

4 Preface

5 About the Authors

6 1 Combinational Circuit Design 1.1 Logic Gates1.1.1 Universal Gate Operation1.1.2 Combinational Logic Circuits1.2 Combinational Logic Circuits Using MSI1.2.1 Adders1.2.2 Multiplexers1.2.3 De-multiplexer1.2.4 Decoders1.2.5 Multiplier1.2.6 Comparators1.2.7 Code Converters1.2.8 Decimal to BCD EncoderReview QuestionsMultiple Choice Questions Reference

7 2 Sequential Circuit Design 2.1 Flip-flops (F/F)2.1.1 S-R F/F2.1.2 D F/F2.1.3 J-K F/F2.1.4 T F/F2.1.5 F/F Excitation Table2.1.6 F/F Characteristic Table2.2 Registers2.2.1 Serial I/P and Serial O/P (SISO)2.2.2 Serial Input and Parallel Output (SIPO)2.2.3 Parallel Input and Parallel Output (PIPO)2.2.4 Parallel Input and Serial Output (PISO)2.3 Counters2.3.1 Synchronous Counter2.3.2 Asynchronous Counter2.3.3 Design of a 3-Bit Synchronous Up-counter2.3.4 Ring Counter2.3.5 Johnson Counter2.4 Finite State Machine (FSM)2.4.1 Mealy and Moore Machine2.4.2 Pattern or Sequence DetectorReview QuestionsMultiple Choice Questions Reference

8 3 Introduction to Verilog HDL 3.1 Basics of Verilog HDL3.1.1 Introduction to VLSI3.1.2 Analog and Digital VLSI3.1.3 Machine Language and HDLs3.1.4 Design Methodologies3.1.5 Design Flow3.2 Level of Abstractions and Modeling Concepts3.2.1 Gate Level3.2.2 Dataflow Level3.2.3 Behavioral Level3.2.4 Switch Level3.3 Basics (Lexical) Conventions3.3.1 Comments3.3.2 Whitespace3.3.3 Identifiers3.3.4 Escaped Identifiers3.3.5 Keywords3.3.6 Strings3.3.7 Operators3.3.8 Numbers3.4 Data Types3.4.1 Values3.4.2 Nets3.4.3 Registers3.4.4 Vectors3.4.5 Integer Data Type3.4.6 Real Data Type3.4.7 Time Data Type3.4.8 Arrays3.4.9 Memories3.5 Testbench ConceptMultiple Choice Questions References

9 4 Programming Techniques in Verilog I 4.1 Programming Techniques in Verilog I4.2 Gate-Level Model of Circuits4.3 Combinational Circuits4.3.1 Adder and Subtractor4.3.2 Multiplexer and De-multiplexer4.3.3 Decoder and Encoder4.3.4 ComparatorReview QuestionsMultiple Choice Questions References

10 5 Programming Techniques in Verilog II 5.1 Programming Techniques in Verilog II5.2 Dataflow Model of Circuits5.3 Dataflow Model of Combinational Circuits5.3.1 Adder and Subtractor5.3.2 Multiplexer5.3.3 Decoder5.3.4 Comparator5.4 Testbench5.4.1 Dataflow Model of the Half Adder and Testbench5.4.2 Dataflow Model of the Half Subtractor and Testbench5.4.3 Dataflow Model of 2 × 1 Mux and Testbench5.4.4 Dataflow Model of 4 × 1 Mux and Testbench5.4.5 Dataflow Model of 2-to-4 Decoder and TestbenchReview QuestionsMultiple Choice Questions References

11 6 Programming Techniques in Verilog II 6.1 Programming Techniques in Verilog II6.2 Behavioral Model of Combinational Circuits6.2.1 Behavioral Code of a Half Adder Using If-else6.2.2 Behavioral Code of a Full Adder Using Half Adders6.2.3 Behavioral Code of a 4-bit Full Adder (FA)6.2.4 Behavioral Model of Multiplexer Circuits6.2.5 Behavioral Model of a 2-to-4 Decoder6.2.6 Behavioral Model of a 4-to-2 Encoder6.3 Behavioral Model of Sequential Circuits6.3.1 Behavioral Modeling of the D-Latch6.3.2 Behavioral Modeling of the D-F/F6.3.3 Behavioral Modeling of the J-K F/F6.3.4 Behavioral Modeling of the D-F/F Using J-K F/F6.3.5 Behavioral Modeling of the T-F/F Using J-K F/F6.3.6 Behavior Modeling of an S-R F/F Using J-K F/FReview QuestionsMultiple Choice Questions References