Suman Lata Tripathi - Digital VLSI Design and Simulation with Verilog

9 Chapter 9Figure 9.1 VLSI design flow at RTL level.Figure 9.2 Example of function implementation with PROM.Figure 9.3 Example of function implementation with PAL.Figure 9.4 Example of function implementation PLA.Figure 9.5 CPLD block diagram.Figure 9.6 PAL-macrocellFigure 9.7 FPGA block diagram.Figure 9.8 2-Input LUT.Figure 9.9 3-Input LUT.Figure 9.10 Digital design flow.

10 Chapter 10Figure 10.1 New project creation on Xilinx ISE simulator.Figure 10.2 New source module creation on Xilinx.Figure 10.3 Xilinx platform for Verilog HDL.Figure 10.4 Behavioral simulation on Xilinx platform.Figure 10.5 4-bit ripple-carry full adder.Figure 10.6 4-bit CLA adder.Figure 10.7 4-bit CSA block diagram.Figure 10.8 Truth table and K-map.Figure 10.9 1.8: 4 × 16 decoder using a 2 × 4 decoder.Figure 10.10 8-bit LFSR.

11 Chapter 1 Table 1.1 T. Table of AND gate. Table 1.2 Truth table of an OR gate. Table 1.3 Truth table of a NOT gate. Table 1.4 Truth table of a NAND gate. Table 1.5 Truth table of a NOR gate. Table 1.6 Truth table of a NAND gate. Table 1.7 Truth table of a half adder. Table 1.8 Truth table of a full adder. Table 1.9 Truth table of the H. subtractor. Table 1.10 Truth table of the full subtractor.Table 1.11 Truth table of the Table 1.12 Truth table of a 1 × 4 de-multiplexer.Table 1.13 Truth table of decoder 2 × 4.Table 1.14 Truth table of a 2-bit comparator.Table 1.15 Octal to Binary converter.Table 1.16 Truth table of a decimal to BCD encoder.

12 Chapter 2Table 2.1 Truth table of an S-R F/F.Table 2.2 Truth table of a D-F/F.Table 2.3 Truth table of a J-K F/F.Table 2.4 Truth table of a T-F/F.Table 2.5 State diagram of a 3-bit counter.Table 2.6 Excitation table of a T-F/F.Table 2.7 State table of a 3-bit counter.Table 2.8 D-F/F excitation table.Table 2.9 State table 1 of sequence 011.Table 2.10 State table 2 of sequence 011.

13 Chapter 4Table 4.1 Half adder.Table 4.2 Full adder.Table 4.3 Half subtractor.Table 4.4 Full subtractor.Table 4.5 2 × 1 multiplexer.Table 4.6 4 × 1 multiplexer.Table 4.7 1 × 2 de-multiplexer.Table 4.8 2-to-4 decoderTable 4.9 4-to-2 encoder.Table 4.10 1-bit magnitude comparator.

14 Chapter 5Table 5.1 Half adder.Table 5.2 Half subtractor.Table 5.4 4 × 1 multiplexer.Table 5.3 2 × 1 multiplexer.Table 5.5 2 × 1 multiplexer.Table 5.6 4 × 1 multiplexer.Table 5.7 2-to-4 decoder.Table 5.8 1-bit magnitude comparator.

15 Chapter 6Table 6.1 Half adder.Table 6.2 Full adder.Table 6.3 2 × 1 multiplexer.Table 6.4 4 × 1 multiplexer.Table 6.5 2-to-4 decoder.Table 6.6 Decoder truth table.Table 6.7 D-F/F truth table.Table 6.8 J-K F/F.

16 Chapter 7Table 7.1 Truth table of a NAND gate.Table 7.2 Truth table of an AND gate.Table 7.3 Truth table of a NOR gate.Table 7.4 Truth table of an OR gate.Table 7.5 Truth table of an XOR gate.Table 7.6 Truth table of an OR gate.Table 7.7 Truth table of a 4 × 1 multiplexer.

17 Chapter 8Table 8.1Table 8.2 Differences between task and function.

18 Chapter 9Table 9.1 Examples of function implementation using a 2-input LUT.Table 9.2 Xilinx FPGA family.

1 Cover

2 Title page Digital VLSI Design and Simulation with Verilog Dr. Suman Lata Tripathi Lovely Professional University, Phagwara, Punjab, India Dr. Sobhit Saxena Lovely Professional University, Phagwara, Punjab, India Dr. Sanjeet Kumar Sinha Lovely Professional University, Phagwara, Punjab, India Dr. Govind Singh Patel IIMT College of Engineering, Greater Noida, UP, India

3 Copyright

4 Table of Contents

5 Preface

6 About the Authors

7 Begin Reading

8 Index

9 End User License Agreement

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Integrated circuits are now growing in importance in every electronic system that needs an efficient VLSI architecture design with low-power consumption, a compress chip area, speed, and operating frequency. The challenge for VLSI system designers is to optimize hardware-software integration for lowering the total cost of product acquisition. So, there is a demand for better technological solutions for advanced VLSI architectures that can be done through hardware description language (HDL). Verilog HDL is one of the programming languages that can provide better solutions in this new era of the VLSI industry. The prefabrication design and analysis of such advanced VLSI architecture can easily be implemented with Verilog HDL using available software tools such as Xilinx and Cadence.

This book mainly deals with the fundamental concepts of digital design along with their design verification with Verilog HDL. It will be a common source of knowledge for beginners as well as research-seeking students working in the area of VLSI design, covering fundamentals of digital design from switch level to FPGA-based implementation using hardware description language (HDL).

The book is summarized in 10 chapters. Chapters 1and 2describe the fundamental concepts behind digital circuit design including combinational and sequential circuit design. Chapters 3to 8 focus on sequential and combinational circuit design using Verilog HDL at different levels of abstraction in Verilog coding. Chapter 9includes implementation of any logic function using a programmable logic device such as PLD, CPLD, FPGA, etc. Chapter 10covers a few real-time examples of digital circuit design using Verilog. Chapter 11focuses on System Verilog, distinct features, computing Verilog and System Verilog with design example.

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