Suman Lata Tripathi - Digital VLSI Design and Simulation with Verilog

12 7 Digital Design Using Switches 7.1 Switch-Level Model7.2 Digital Design Using CMOS Technology7.3 CMOS Inverter7.4 Design and Implementation of the Combinational Circuit Using Switches7.4.1 Types of Switches7.4.2 CMOS Switches7.4.3 Resistive Switches7.4.4 Bidirectional Switches7.4.5 Supply and Ground Requirements7.5 Logic Implementation Using Switches7.5.1 Digital Design with a Transmission Gate7.6 Implementation with Bidirectional Switches7.6.1 Multiplexer Using Switches7.7 Verilog Switch-Level Description with Structural-Level Modeling7.8 Delay Model with SwitchesReview QuestionsMultiple Choice Questions References

13 8 Advance Verilog Topics 8.1 Delay Modeling and Programming8.1.1 Delay Modeling8.1.2 Distributed-Delay Model8.1.3 Lumped-Delay Model8.1.4 Pin-to-Pin-Delay Model8.2 User-Defined Primitive (UDP)8.2.1 Combinational UDPs8.2.2 Sequential UDPs8.2.3 Shorthands in UDP8.3 Task and Function8.3.1 Difference between Task and Function8.3.2 Syntax of Task and Function Declaration8.3.3 Invoking Task and Function8.3.4 Examples of Task Declaration and Invocation8.3.5 Examples of Function Declaration and InvocationReview QuestionsMultiple Choice Questions References

14 9 Programmable and Reconfigurable Devices 9.1 Logic Synthesis9.1.1 Technology Mapping9.1.2 Technology Libraries9.2 Introduction of a Programmable Logic Device9.2.1 PROM, PAL and PLA9.2.2 SPLD and CPLD9.3 Field-Programmable Gate Array9.3.1 FPGA Architecture9.4 Shannon’s Expansion and Look-up Table9.4.1 2-Input LUT9.4.2 3-Input LUT9.5 FPGA Families9.6 Programming with FPGA9.6.1 Introduction to Xilinx Vivado Design Suite for FPGA-Based Implementations9.7 ASIC and Its ApplicationsReview QuestionsMultiple Choice Questions References

15 10 Project Based on Verilog HDLs 10.1 Project Based on Combinational Circuit Design Using Verilog HDL10.1.1 Full Adder Using Switches at Structural Level Model10.1.2 Ripple-Carry Full Adder (RCFA)10.1.3 4-bit Carry Look-ahead Adder (CLA)10.1.4 Design of a 4-bit Carry Save Adder (CSA)10.1.5 2-bit Array Multiplier10.1.6 2 × 2 Bit Division Circuit Design10.1.7 2-bit Comparator10.1.8 16-bit Arithmetic Logic Unit10.1.9 Design and Implementation of 4 × 16 Decoder Using 2 × Decoder10.2 Project Based on Sequential Circuit Design Using Verilog HDL10.2.1 Design of 4-bit Up/down Counter10.2.2 LFSR Based 8-bit Test Pattern Generator10.3 Counter Design10.3.1 Random Counter that Counts Sequence like 2,4,6,8,2,8…and so On10.3.2 Use of Task at the Behavioral-Level Model10.3.3 Traffic Signal Light Controller10.3.4 Hamming Code(h,k) Encoder/DecoderReview QuestionsMultiple Choice Questions References

16 11 SystemVerilog 11.1 Introduction11.2 Distinct Features of SystemVerilog11.2.1 Data Types11.2.2 Arrays11.2.3 Typedef11.2.4 Enum11.3 Always_type11.4 $log2c() Function11.5 System-Verilog as a Verification LanguageReview QuestionsMultiple Choice Questions Reference

17 Index

18 End User License Agreement

1 Chapter 1Figure 1.1 Symbol of an AND gate.Figure 1.2 Symbol for an OR gate.Figure 1.3 Symbol for a NOT gate.Figure 1.4 Symbol for a NAND gate.Figure 1.5 Symbol for a NOR gate.Figure 1.6 Symbol for a NAND gate.Figure 1.7 Diagram of a combinational logic circuit.Figure 1.8 Block diagram of a H. adder.Figure 1.9 Circuit diagram of a half adder.Figure 1.10 Block diagram of a full adder.Figure 1.11 Full adder logic block.Figure 1.12 Half subtractor.Figure 1.13 Half subtractor logic block.Figure 1.14 Block diagram of the full subtractor.Figure 1.15 Full subtractor logic block.Figure 1.16 Block diagram of the multiplexer.Figure 1.17 Logic diagram of the multiplexer.Figure 1.18 Implementation of function.Figure 1.19 Block diagram of the de-multiplexer.Figure 1.20 1 × 4 de-multiplexer using logic gates.Figure 1.21 Block diagram of a 2 × 4 decoder.Figure 1.22 Logic diagram of a 2 × 4 decoder.Figure 1.23 Implementation of functions using the decoder.Figure 1.24 Block diagram of a 2-bit binary multiplier.Figure 1.25 Circuit diagram of a 2-bit multiplier.Figure 1.26 2-bit comparator block.

2 Chapter 2Figure 2.1 Clocked S-R F/F.Figure 2.2 Clocked D-F/F.Figure 2.3 Clocked J-K F/F.Figure 2.4 Master-slave of a J-K F/F.Figure 2.5 Clocked T-F/F.Figure 2.6 Excitation table of a) S-R, b) D, c) J-K and d) D- F/F.Figure 2.7 Characteristic table a) D-F/F and b) T-F/F.Figure 2.8 SISO shift register block diagram.Figure 2.9 SIPO shift register block diagram.Figure 2.10 PIPO shift register block diagram.Figure 2.11 PISO shift register block diagram.Figure 2.12 3-bit Synchronous up-counter with J-K F/F.Figure 2.13 3-bit ripple counter (up-counter).Figure 2.14 State diagram of a 3-bit up-counter.Figure 2.15 3-bit up-counter logic block.Figure 2.16 4-bit ring counter using D-F/F.Figure 2.17 4-bit Johnson counter using D-F/F.Figure 2.18 Mealy machine.Figure 2.19 Moore machine.Figure 2.20 Design 011 sequence using a Mealy machine.Figure 2.21 State-diagram representation of Moore model.Figure 2.22 Sequence circuit of 011 Mealy sequences.

3 Chapter 3Figure 3.1 Top-down design methodology.Figure 3.2 Bottom-up design methodology.Figure 3.3 Design flow chart.

4 Chapter 4Figure 4.1 Logic circuit.Figure 4.2 Logic circuit.Figure 4.3 Block diagram of a half adder.Figure 4.4 Logic circuit of half adder.Figure 4.5 Logic circuit of half adder using a NAND gate.Figure 4.6 Logic circuit of half adder using NOR gate.Figure 4.7 Block diagram of a full adder.Figure 4.8 Logic circuit of a full adder.Figure 4.9 Block diagram of a half subtractor.Figure 4.10 Logic circuit of a full subtractor.Figure 4.11 Logic circuit of a half subtractor using a NAND gate.Figure 4.12 Logic circuit of the half subtractor using a NOR gate.Figure 4.13 Block diagram of a full subtractor.Figure 4.14 Logic circuit of a full subtractor.Figure 4.15 Block diagram of a 2 × 1 multiplexer.Figure 4.16 Logic circuit of a 2 × 1 multiplexer.Figure 4.17 Block diagram of a 4 × 1 multiplexer.Figure 4.18 Logic circuit of a 4 × 1 multiplexer.Figure 4.19 Block diagram of 1 × 2 de-multiplexer.Figure 4.20 Logic circuit of a 1 × 2 de-multiplexer.Figure 4.21 Block diagram of 2-to-4 decoder.Figure 4.22 Logic circuit of a 2-to-4 decoder.Figure 4.23 Block diagram of 4-to-2 encoder.Figure 4.24 Logic circuit of 4-to-2 encoder.Figure 4.25 Logic circuit of a 1-bit magnitude comparator.

5 Chapter 5Figure 5.1 Block diagram of 2 × 1 multiplexer.Figure 5.2 Block diagram of 4 × 1 multiplexer.

6 Chapter 6Figure 6.1 Logic circuit of a full adder [1].Figure 6.2 Block diagram of a 4-bit full adder [1].Figure 6.3 Logic circuit of 4 × 1 multiplexer.Figure 6.4 Block diagram of a 2-to-4 decoder.Figure 6.5 Block diagram of a 4-to-2 decoder.Figure 6.6 Block diagram of the D-Latch.Figure 6.7 Block diagram of a D-F/F.Figure 6.8 Block diagram of the J-K F/F.Figure 6.9 Block diagram of the D-F/F using J-K F/F.Figure 6.10 Block diagram of the J-K F/F using T-F/F.Figure 6.11 Block diagram of an S-R F/F using J-K F/F.

7 Chapter 7Figure 7.1 CMOS design with pull-up and pull-down network.Figure 7.3 MOS switches (a) NMOS (b) PMOS.Figure 7.4 Symbol of a CMOS switch.Figure 7.5 Resistive Switches (a) tran (b) tranif1 (c) tranif0.Figure 7.2 CMOS inverter.Figure 7.6 NAND gate implantation at transistor level.Figure 7.7 AND gate using MOS switches.Figure 7.8 NOR gate using switches.Figure 7.9 OR gate using switches.Figure 7.10 XOR gate using switch.Figure 7.11 2 × 1 Multiplexer block.Figure 7.12 2 × 1 Multiplexer using a CMOS switch.Figure 7.13 4 × 1-multiplexer block.Figure 7.14 4 × 1-multiplexer using switches.Figure 7.15 1-bit full-adder implementation using a 4 × 1 multiplexer.

8 Chapter 8Figure 8.1 A simple combinational circuit indicating distributed delay.Figure 8.2 A simple combinational circuit indicating lumped delay.Figure 8.3 Possible path from individual input to output.