Liliana Andrade - Multi-Processor System-on-Chip 1

9 Chapter 9Figure 9.1. A traditional synchronous bus, in this case the implementation of an...Figure 9.2. Arteris switch fabric network (Arteris IP 2020)Figure 9.3. NoC layer mapping summary (Arteris IP 2020)Figure 9.4. The NoC on the left has a floorplan-unfriendly topology, whereas the...Figure 9.5. Pipeline stages are required in a path to span a particular distance...Figure 9.6. Single-event effect (SEE) error hierarchy diagram (ISO26262-11 2018b...Figure 9.7. Failure mode effects and diagnostic analysis (FMEDA) includes analys...Figure 9.8. A cache coherent NoC interconnect allows the integration of IP using...Figure 9.9. NoC interconnects enable easier creation of hard macro tiles that ca...Figure 9.10. Hierarchical coherency macros enable massive scalability of cache c...Figure 9.11. An AUTOSAR MCAL showing how NoC configuration information will be u...

10 Chapter 10Figure 10.1. Energy efficiency improvement by near-threshold computingFigure 10.2. Block diagram of the SCM with an R × C-bit capacityFigure 10.3. An example of SCM structures (R = 4 ,C = 4 )Figure 10.4. Energy measurement results for two memories with a 256 × 32 capacit...Figure 10.5. Minimum energy point curvesFigure 10.6. Energy and delay contoursFigure 10.7. Minimum energy point in near- or sub-threshold regionFigure 10.8. Minimum energy point in super-threshold regionFigure 10.9. The concept of minimum energy point tracking algorithmFigure 10.10. An OS-based algorithm for MEPT

11 Chapter 11Figure 11.1. Tasks in a heterogeneous computing architecture communicate with ea...Figure 11.2. Hardware context switchonatask with FIFO-based communication channe...Figure 11.3. Modified communication channel to support hardware context switchin...Figure 11.4. The proposed communication protocol in hardware context switchingFigure 11.5. FIFOs in the communication channelFigure 11.6. Reconfigurable architecture with the proposed communication structu...Figure 11.7. Hardware context switch scenario in the experimentsFigure 11.8. Comparison of hardware context switch (preemption) time between CS ...Figure 11.9. Hardware task migration between heterogeneous reconfigurable SoCsFigure 11.10. Task migration timeline

1 Cover

2 Table of Contents

3 Title Page SCIENCES Electronics Engineering , Field Director – Francis Balestra Design Methodologies and Architecture , Subject Head – Ahmed Jerraya

4 Copyright First published 2020 in Great Britain and the United States by ISTE Ltd and John Wiley & Sons, Inc. Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address: ISTE Ltd 27-37 St George’s Road London SW19 4EU UK www.iste.co.uk John Wiley & Sons, Inc. 111 River Street Hoboken, NJ 07030 USA www.wiley.com © ISTE Ltd 2020 The rights of Liliana Andrade and Frédéric Rousseau to be identified as the authors of this work have been asserted by them in accordance with the Copyright, Designs and Patents Act 1988. Library of Congress Control Number: 2020940076 British Library Cataloguing-in-Publication Data A CIP record for this book is available from the British Library ISBN 978-1-78945-021-7 ERC code: PE6 Computer Science and Informatics PE6_1 Computer architecture, pervasive computing, ubiquitous computing PE6_10 Web and information systems, database systems, information retrieval and digital libraries, data fusion PE7 Systems and Communication Engineering PE7_2 Electrical engineering: power components and/or systems

5 Foreword

6 Acknowledgments

7 Begin Reading

8 List of Authors

9 Author Biographies

10 Index

11 End User License Agreement

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