Christopher Hallinan: Embedded Linux Primer: A Practical, Real-World Approach

A typical SDRAM chip requires one refresh cycle for each row. Each row must be refreshed in the minimum time specified by the manufacturer. In the chip referenced in Section D.4.1, "Suggestions for Additional Reading," the manufacturer specifies that 8,192 rows must be refreshed every 64 milliseconds. This requires generating a refresh cycle every 7.8 microseconds to meet the specifications for this particular device.

SDRAM devices are quite complex. This appendix presented a very simple example to help you navigate the complexities of SDRAM controller setup. The SDRAM controllers perform a critical function and must be properly set up. There is no substitute to diving into a specification and digesting the information presented. The two example documents referenced in this appendix are excellent starting points.

AMCC 405GP Embedded Processor User's Manual

AMCC Corporation

www.amcc.com/Embedded/

Micron Technology, Inc.

Synchronous DRAM MT48LC64M4A2 Data Sheet

http://download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf

Several locations on the Web focus on Linux development. Here is a list of the most important websites for the various architectures and projects:

Primary kernel source tree

www.kernel.org

Primary kernel GIT repository

www.kernel.org/git

PowerPC-related development and mailing lists

http://ozlabs.org/

MIPS-related developments

www.linux-mips.org

ARM-related Linux development

www.arm.linux.org.uk

Primary home for a huge collection of open-source projects

http://sourceforge.net

Hundreds, if not thousands, of mailing lists cater to every aspect of Linux and open-source development. Here are a few to consider. Make sure you familiarize yourself with mailing list etiquette before posting to these lists.

Most of these lists maintain archives that are searchable. This is the first place that you should consult. In a great majority of the cases, your question has already been asked and answered. Start your reading here, for advice on how to best use the public mail lists:

The Linux Kernel Mailing List FAQ

www.tux.org/lkml

List server serving various Linux kernel-related mail lists

http://vger.kernel.org

Linux Kernel Mailingvery high volume, kernel development only

http://vger.kernel.org/vger-lists.html#linux-kernel

Many news sites are worth browsing occasionally. Some of the more popular are ­listed here.

LinuxDevices.com

www.linuxdevices.com

PowerPC News and other information

http://penguinppc.org

General Linux News and Developments

www.lwn.net

The following public website contains useful information and education focusing on legal issues around open source.

www.open-bar.org

; bdiGDB configuration file for the UEI PPC 5200 Board

; Revision 1.0

; Revision 1.1 (Added serial port setup)

; -----------------------------------------------------------

; 4 MB Flash (Am29DL323)

; 128 MB Micron DDR DRAM

;

[INIT]

; init core register

WREG MSR 0x00003002 ;MSR : FP,ME,RI

WM32 0x80000000 0x00008000 ;MBAR : internal registers at 0x80000000

; Default after RESET, MBAR sits at 0x80000000

; because it's POR value is 0x0000_8000 (!)

WSPR 311 0x80000000 ; MBAR : save internal register offset

; SPR311 is the MBAR in G2_LE

WSPR 279 0x80000000 ;SPRG7: save internal memory offsetReg: 279

; Init CDM (Clock Distribution Module)

; Hardware Reset config {

; ppc_pll_cfg[0..4] = 01000b

: XLB:Core -> 1:3

: Core:f(VCO) -> 1:2

: XLB:f(VCO) -> 1:6

;

; xlb_clk_sel = 0 -> XLB_CLK=f(sys) / 4 = 132 MHz

;

; sys_pll_cfg_1 = 0 -> NOP

; sys_pll_cfg_0 = 0 -> f(sys) = 16x SYS_XTAL_IN = 528 MHz

; }

;

; CDM Configuration Register

WM32 0x8000020c 0x01000101

; enable DDR Mode

; ipb_clk_sel = 1 -> XLB_CLK / 2 (ipb_clk = 66 MHz)

; pci_clk_sel = 01 -> IPB_CLK/2

; CS0 Flash

WM32 0x80000004 0x0000ff00 ;CS0 start = 0xff000000 - Flash memory is on

CS0

WM32 0x80000008 0x0000ffff ;CS0 stop = 0xffffffff

; IPBI Register and Wait State Enable

WM32 0x80000054 0x00050001 ;CSE: enable CS0, disable CSBOOT,

;Wait state enable\

; CS2 also enabled

WM32 0x80000300 0x00045d30 ;BOOT ctrl

; bits 0-7: WaitP (try 0xff)

; bits 8-15: WaitX (try 0xff)

; bit 16: Multiplex or non-mux'ed (0x0 = non-muxed)

; bit 17: reserved (Reset value = 0x1, keep it)

; bit 18: Ack Active (0x0)

; bit 19: CE (Enable) 0x1

; bits 20-21: Address Size (0x11 = 25/6 bits)

; bits 22:23: Data size field (0x01 = 16-bits)

; bits 24:25: Bank bits (0x00)

; bits 26-27: WaitType (0x11)

; bits 28: Write Swap (0x0 = no swap)

; bits 29: Read Swap (0x0 = no swap)

; bit 30: Write Only (0x0 = read enable)

; bit 31: Read Only (0x0 = write enable)

; CS2 Logic Registers

WM32 0x80000014 0x0000e00e

WM32 0x80000018 0x0000efff

; LEDS:

; LED1 - bits 0-7

; LED2 - bits 8-15

; LED3 - bits 16-23

; LED4 - bits 24-31

; off = 0x01

; on = 0x02

; mm 0xe00e2030 0x02020202 1 (all on)

; mm 0xe00e2030 0x01020102 1 (2 on, 2 off)

WM32 0x80000308 0x00045b30 ; CS2 Configuration Register

; bits 0-7: WaitP (try 0xff)

; bits 8-15: WaitX (try 0xff)

; bit 16: Multiplex or non-mux'ed (0x0 =

non-muxed)

; bit 17: reserved (Reset value = 0x1, keep it)

; bit 18: Ack Active (0x0)

; bit 19: CE (Enable) 0x1

; bits 20-21: Address Size (0x10 = 24 bits)

; bits 22:23: Data size field (0x11 = 32-bits)

; bits 24:25: Bank bits (0x00)

; bits 26-27: WaitType (0x11)

; bits 28: Write Swap (0x0 = no swap)

; bits 29: Read Swap (0x0 = no swap)

; bit 30: Write Only (0x0 = read enable)

; bit 31: Read Only (0x0 = write enable)

WM32 0x80000318 0x01000000 ; Master LPC Enable

;

; init SDRAM controller

;

; For the UEI PPC 5200 Board,

; Micron 46V32M16-75E (8 MEG x 16 x 4 banks)