Philippe Darche - Microprocessor 1

3 Chapter 3Figure 3.1. Description of the computation of a factorial via dataflow graphFigure 3.2. Positioning of the computation model in relation to the architectureFigure 3.3. Multi-level architectural conceptsFigure 3.4. Computer design layers based on Blaauw and Brooks (1996)Figure 3.5. Y-diagram (Gajski and Kuhn 1983)Figure 3.6. Hierarchical structure of a computerFigure 3.7. Different levels of abstraction of computer architecture based on Si...Figure 3.8. Abstract and concrete hierarchical aspects of an architectureFigure 3.9. The concept of computer architecture according to Sima et al. (1997)Figure 3.10. Layered design of a computerFigure 3.11. Positioning of architecture for four historic architectures (Corpor...Figure 3.12. Architecture according to von Neumann (1945)Figure 3.13. Von Neumann machine with its five functional unitsFigure 3.14. Simplified functional organization of the IAS machineFigure 3.15. Functional organization of a von Neumann machineFigure 3.16. Functional organization of the IBM 701 (based on Frizzell (1953), m...Figure 3.17. Infinite two-phase execution cycleFigure 3.18. Modern view of a von Neumann computerFigure 3.19. The three communications busesFigure 3.20. The three functional units of a microprocessorFigure 3.21. Internal circulation of information inside a microprocessorFigure 3.22. Microarchitecture of bus-based microprocessorsFigure 3.23. Decoding of an instruction by a hardwired sequencerFigure 3.24. Basic steps of the basic execution cycleFigure 3.25. Execution cycle flowchartFigure 3.26. Functional steps to execute an instructionFigure 3.27. Execution cycle described with different forms of accessFigure 3.28. Information flow in a processorFigure 3.29. Internal organization of a bus (control signals not shown)Figure 3.30. Functional internal organization of Intel 8080A microprocessors wit...Figure 3.31. Two variations of a double internal bus organization (CU and contro...Figure 3.32. Internal functional organization of the Motorola MC6800 microproces...Figure 3.33. Functional internal organization of the PACE microprocessor from NS...Figure 3.34. Internal three-bus organization (CU and control signals not shown)Figure 3.35. Pure Harvard architectureFigure 3.36. Example of a modified Harvard architecture (x86 family)Figure 3.37. Simplified architecture of a SPARC ®family processorFigure 3.38. The four basic approaches to ILPFigure 3.39. Simplified classification of TLP architecturesFigure 3.40. Variation of characteristics over time (based on (Leavitt 2012))Figure 3.41. Microphotograph of an Intel Sandy Bridge quad-core i7 (source: Inte...Figure 3.42. Classes of instruction set architectures with examplesFigure 3.43. Zero-address stack architecture (from Nurmi (2007), modified)Figure 3.44. One-address architecture, with accumulator (from (Nurmi 2007), modi...Figure 3.45. Architecture with two (a) and three (b) register references (from N...Figure 3.46. Memory-register architectures (from Nurmi (2007), modifiedFigure 3.47. Three-address architecture (from Nurmi (2007), modified

1 Chapter 1 Table 1.1. Generations of calculating machines and computers based on component ... Table 1.2. Reference computers for generations 1 and 2 Table 1.3. The main computers from this generation Table 1.4. Primary computers in this generation Table 1.5a. Classification of generations of integrated circuits according to va... Table 1.5b. Classification of generations of integrated circuits according to va... Table 1.5c. Classification of generations of integrated circuits according to va... Table 1.6. Classification of generations of integrated circuits adopted Table 1.7. Comparison of characteristics between computing resources (from Suri ...Table 1.8a. Generations of computers and main featuresTable 1.8b. Generations of computers and main features (continued)

2 Chapter 2Table 2.1. Vocabulary describing a packet of bits (Darche 2012)Table 2.2. New prefixes of measurement units for memory

3 Chapter 3Table 3.1. Runtime models and computer categories (Treleaven and Lima 84, van de...Table 3.2. Characteristics of the main models of computation (according to Sima ...Table 3.3. Characteristics of the primary computation models (according to Sima ...Table 3.4. Characteristics of the main computation models – continued (based on ...Table 3.5. Characteristics of architecture classes (according to Hennessy and Pa...

1 Cover

2 Table of Contents

3 Title Page

4 Copyright First published 2020 in Great Britain and the United States by ISTE Ltd and John Wiley & Sons, Inc. Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address: ISTE Ltd 27-37 St George’s Road London SW19 4EU UK www.iste.co.uk John Wiley & Sons, Inc. 111 River Street Hoboken, NJ 07030 USA www.wiley.com © ISTE Ltd 2020 The rights of Philippe Darche to be identified as the author of this work have been asserted by him in accordance with the Copyright, Designs and Patents Act 1988. Library of Congress Control Number: 2020938715 British Library Cataloguing-in-Publication Data A CIP record for this book is available from the British Library ISBN 978-1-78630-563-3

5 Quotation

6 Preface

7 Introduction

8 Begin Reading

9 Conclusion of Volume 1

10 Exercises

11 Acronyms

12 References

13 Index

14 End User License Agreement

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