Philippe Darche - Microprocessor 5

1 Cover

2 Title page Series Editor Jean-Charles Pomerol

3 Copyright First published 2020 in Great Britain and the United States by ISTE Ltd and John Wiley & Sons, Inc. Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address: ISTE Ltd 27-37 St George’s Road London SW19 4EU UK www.iste.co.uk John Wiley & Sons, Inc. 111 River Street Hoboken, NJ 07030 USA www.wiley.com © ISTE Ltd 2020 The rights of Philippe Darche to be identified as the author of this work have been asserted by him in accordance with the Copyright, Designs and Patents Act 1988. Library of Congress Control Number: 2020943158 British Library Cataloguing-in-Publication Data A CIP record for this book is available from the British Library ISBN 978-1-78630-651-7

4 Quotation

5 Preface

6 Introduction

7 PART 1 PART 1 The first part of this last volume is divided into two chapters. The first presents the software development chain, and the second illustrates the hardware and software tools used in development and testing. 1 Development Chain 1.1. Layers of languages, stages of development and tools 1.2. Fundamental software tools for development 1.3. Assembly language 1.4. Conclusion 2 Debugging and Testing 2.1. Hardware support 2.2. Debugging 2.3. Testing 2.4. Conclusion

8 PART 2 3 Changes in the Organization of the Earliest Microcomputers 3.1. Apple II 3.2. IBM PCs 3.3. Chipset 3.4. Motherboard architectures 3.5. Evolution of microcomputer firmware 3.6. Conclusion

9 Conclusion of Volume 5

10 Exercises

11 Acronyms

12 References

13 Index

14 End User License Agreement

1 Chapter 1 Figure 1.1. Example of lines from a program written in 80x86 assembly language Figure 1.2. Levels of languages in computing Figure 1.3. Development chain for a program written in a compilable high-level l... Figure 1.4. Relationship between the type and levels of languages Figure 1.5. Software development chain in a mixed-language environment and with ... Figure 1.6. API and ABI interfaces and Hardware Abstraction Layer. For a color v... Figure 1.7. Information flow for assembly Figure 1.8. Functional phases of assembly Figure 1.9. Example of a symbol table extracted from the listing file in Figure ... Figure 1.10. Example of a listing file generated by tasm (symbol table in Figure... Figure 1.11. I/O for link editing Figure 1.12. Types of libraries Figure 1.13. Example of a source file for a microcontroller from the Atmel AVR f...Figure 1.14. Example of a program with macro-instruction and then expansionFigure 1.15. Development chain with macro-management

2 Chapter 2Figure 2.1. The Intel SDK85 evaluation kit. For a color version of this figure, ...Figure 2.2. Communication between host and target systems. For a color version o...Figure 2.3. The Atmel STK500 evaluation kit. For a color version of this figure,...Figure 2.4. Microcontroller with integrated EPROM seen through the package’s qua...Figure 2.5. ISP and PDI interfaces for the Atmel STK600 evaluation kitFigure 2.6. Management state diagram compatible with the IEEE 1149.1 standardFigure 2.7. Compatibility between standardized instructions and target registersFigure 2.8. Hardware emulation chain. For a color version of this figure, see ww...Figure 2.10. The Atmel Studio simulator. For a color version of this figure, see...Figure 2.11. The Borland TurboDebugger. For a color version of this figure, see ...Figure 2.12. Debugging link with BDM access (HCS08/RS08 target system). For a co...Figure 2.13. BDM interface signalsFigure 2.14. Debugging connection using a JTAG port. For a color version of this...Figure 2.15. A chain of test modules.Figure 2.16. JTAG logic around the initial coreFigure 2.17. A typical boundary-scan register cell (a) with an example implement...Figure 2.18. JTAG connector examplesFigure 2.19. Components required by the standardFigure 2.20. Redirected debugging with gdb. For a color version of this figure, ...

3 Chapter 3Figure 3.1. Original Apple II motherboard (Rev. 0). For a color version of this ...Figure 3.2. Apple II block diagram (Gayler 1983)Figure 3.3. Top view of Apple II expansion slot (Gayler 1983)Figure 3.4. Installed daughter boards (unknown source). For a color version of t...Figure 3.5. IBM 5150 (original PC) motherboard. For a color version of this figu...Figure 3.6. Overview of the IBM 5150 motherboard (IBM 1984a). For a color versio...Figure 3.7. Overhead view of the 5150 bus expansion slot and its signals (IBM 19...Figure 3.8. IBM 5160 motherboard (PC XT). For a color version of this figure, se...Figure 3.9. Overview of the PC XT motherboard (IBM 1983). For a color version of...Figure 3.10. Topography of main memory (Figure 2.110 in Darche (2012) completed)Figure 3.11. IBM 5170 type 1 motherboard (PC AT). For a color version of this fi...Figure 3.12. Overview of the PC AT type 1 motherboard (IBM 1984b). For a color v...Figure 3.13. Overview of the PC AT type 2 motherboard (IBM 1986). For a color ve...Figure 3.14. ISA bus expansion slot extended to 16 bits and its 16-bit expansion...Figure 3.15. AT block diagram (IBM 1984b)Figure 3.16. Architecture based on the 82420 chipset for use with the 80486 (Sla...Figure 3.17. Architecture based on the 82430 chipset for use with the Pentium (I...Figure 3.18. Components in the 82430 chipset managing the EISA (Gwennap 1993) © ...Figure 3.19. Internal overview of a super I/O component: the PC87306 from NSFigure 3.20. Organization of a motherboard with an Intel 450KX/GX chipset (Intel...Figure 3.21. Implementation of AGP with the 440BX chipset (source: Intel)Figure 3.22. Intel HUB architectureFigure 3.23. DMI link connecting the MCH to the ICH: the 915PFigure 3.24. HyperTransport TunnelFigure 3.25. Timeline of the main motherboard form factorsFigure 3.26. Current PRIME B250-PRO motherboard (source: Asus – 2018, completed)...Figure 3.27. The different functional layers of an old-generation PC microcomput...Figure 3.28. EFI software location

1 Chapter 1 Table 1.1. Language comparison (based on Jones (1986)) Table 1.2. Address space operators in the IEEE 694-1985 standardTable 1.3. Standardized format suffixes

2 Chapter 2Table 2.1. Incremental characteristics of classes of debuggersTable 2.2. Generic characteristics of a debugging monitorTable 2.3. Primary characteristics of the HC08’s monitor mode (Motorola)Table 2.4. Characteristics of the background debugging mode for Motorola HCS08 a...Table 2.5. Comparison of functionality between various debugging tools (1/2)Table 2.6. Comparison of functionality between various debugging tools (2/2)Table 2.7. Classification of debugging approaches (Chen et al. 2002). F: Foregro...

3 Chapter 3Table 3.1. Characteristics of Intel 430 chipset family (except for the mobile 43...Table 3.2. Characteristics of the first Intel chipsets in the 450/440 familiesTable 3.3. Characteristics of the first Intel chipsets in the 450/440 families (...Table 3.4. Summary of various form factors